[PATCH 1/4] arm: dts: rockchip: rk3566: Remove unnecessary clks from rgxx3
Chris Morgan
macroalpha82 at gmail.com
Mon Feb 5 19:58:52 CET 2024
From: Chris Morgan <macromorgan at hotmail.com>
Remove unnecessary clock frequency defines from the RGxx3 u-boot dts.
Move the necessary defines to the RGxx3 main dts file.
Signed-off-by: Chris Morgan <macromorgan at hotmail.com>
---
.../arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 31 -------------------
arch/arm/dts/rk3566-anbernic-rgxx3.dts | 7 +++++
2 files changed, 7 insertions(+), 31 deletions(-)
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
index f986e1941e..ef4f81500b 100644
--- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
@@ -15,37 +15,6 @@
};
};
-&cru {
- assigned-clocks =
- <&pmucru CLK_RTC_32K>,
- <&pmucru PLL_PPLL>,
- <&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
- <&cru PLL_GPLL>,
- <&cru ACLK_BUS>, <&cru PCLK_BUS>,
- <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
- <&cru HCLK_TOP>, <&cru PCLK_TOP>,
- <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
- <&cru CPLL_500M>, <&cru CPLL_333M>,
- <&cru CPLL_250M>, <&cru CPLL_125M>,
- <&cru CPLL_100M>, <&cru CPLL_62P5M>,
- <&cru CPLL_50M>, <&cru CPLL_25M>;
- assigned-clock-rates =
- <32768>,
- <200000000>,
- <100000000>, <1000000000>,
- <1188000000>,
- <150000000>, <100000000>,
- <500000000>, <400000000>,
- <150000000>, <100000000>,
- <300000000>, <150000000>,
- <500000000>, <333333333>,
- <250000000>, <125000000>,
- <100000000>, <62500000>,
- <50000000>, <25000000>;
- assigned-clock-parents =
- <&pmucru CLK_RTC32K_FRAC>;
-};
-
&dsi_dphy0 {
status = "okay";
};
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
index 404dddfafb..9e0aa9e63b 100644
--- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
@@ -16,3 +16,10 @@
"anbernic,rg353v", "anbernic,rg353vs",
"anbernic,rg503", "rockchip,rk3566";
};
+
+&cru {
+ assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
+ <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+ assigned-clock-rates = <32768>, <1200000000>,
+ <200000000>, <241500000>;
+};
--
2.34.1
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