[PATCH 0/5] riscv: mbv: Enhance MB-V support with also enabling SPL
Michal Simek
michal.simek at amd.com
Wed Feb 14 12:52:28 CET 2024
Hi,
enhance MB-V support with SPL configuration to support OpenSBI.
All of that changes are out of generic Risc-V support that's why happy to
take it via my tree. Please let me know if you want this to take via riscv
subtree.
Thanks,
Michal
Michal Simek (5):
riscv: mbv: Align addresses with default DT
riscv: mbv: Enable REMAKE_ELF by default
riscv: mbv: Switch to OF_SEPARATE with fixed address
riscv: mbv: Moving little_endian variable to data section
riscv: mbv: Enable SPL and binman
arch/riscv/dts/xilinx-mbv32.dts | 3 +++
board/xilinx/Kconfig | 1 +
board/xilinx/common/board.c | 8 ++++++++
board/xilinx/mbv/Kconfig | 14 ++++++++++++--
board/xilinx/mbv/board.c | 10 ++++++++++
configs/xilinx_mbv32_defconfig | 23 ++++++++++++++++++-----
configs/xilinx_mbv32_smode_defconfig | 25 ++++++++++++++++++++-----
drivers/serial/serial_xuartlite.c | 2 +-
8 files changed, 73 insertions(+), 13 deletions(-)
--
2.36.1
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