[PATCH] arm: dts: k3-am625-verdin-r5: Change CPU frequency to 1000MHz

[Vignesh Raghavendra]

On 19/02/24 18:04, Vitor Soares wrote:
> From: Vitor Soares <vitor.soares at toradex.com>
> 
> The same U-Boot binary is compatible with multiple Verdin AM62 board
> variants. However, some of the SoC models can only operate at a maximum
> speed of 1 GHz.
> 
> Previously, the boards with lower-speed grades were running at
> overclocked speeds, leading to kernel complaints about unsupported
> configurations.
> 
> To resolve this issue, the operating speed has been decreased to the
> maximum allowable value across all Verdin AM62 board variants. As a
> result, there is a regression in overall boot time, increasing by around
> 200 milliseconds for the faster SoC variant.
> 

Patch as such is fine. But one way to avoid boot regression is to fixup
the clock freq using based on speed grade identified by
k3_get_speed_grade() and freq mapping table for each letter as show in
datasheet [0]

This may need VDD_CORE voltage information via PMIC driver. Even w/o
that could at least bump to 1.25Ghz safely.

[0] https://www.ti.com/lit/ds/symlink/am625.pdf
Table 7-1. Device Speed Grades


> Signed-off-by: Vitor Soares <vitor.soares at toradex.com>
> ---
>  arch/arm/dts/k3-am625-verdin-r5.dts | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts
> index 305d199678..6b03e7405a 100644
> --- a/arch/arm/dts/k3-am625-verdin-r5.dts
> +++ b/arch/arm/dts/k3-am625-verdin-r5.dts
> @@ -23,7 +23,7 @@
>  		 */
>  		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 20>;
>  		assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 22>;
> -		assigned-clock-rates = <200000000>, <1200000000>, <25000000>;
> +		assigned-clock-rates = <200000000>, <1000000000>, <25000000>;
>  		clocks = <&k3_clks 61 0>;
>  		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
>  				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,

-- 
Regards
Vignesh