[PATCH] arch: mach-k3: Fix incorrect mapping of higher DDR addresses as device memory

[Nishanth Menon]

On 14:15-20240109, Sekhar Nori wrote:
> Entry for physical address 0x500000000 in memory map table for MMU
> configuration is spilling over and inadvertently making DDR available at
> higher address (above 4GB address space) get mapped as device memory
> (nGnRnE).
> 
> Fix this by adjusting entry size. Tested on AM62A SK. Before this patch:
> 
> => time crc32 0x881000000 0x20000000
> crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca
> 
> time: 1 minutes, 14.716 seconds
> 
> After patch:
> 
> => time crc32 0x881000000 0x20000000
> crc32 for 881000000 ... 8a0ffffff ==> 7f34d7ca
> 
> time: 2.710 seconds
> 
> Acked-by: Andrew Davis <afd at ti.com>
> Signed-off-by: Sekhar Nori <nsekhar at ti.com>
> ---
> Applies to u-boot/next
> 
>  arch/arm/mach-k3/arm64-mmu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
> index b4308205b2..0e07b1b7ce 100644
> --- a/arch/arm/mach-k3/arm64-mmu.c
> +++ b/arch/arm/mach-k3/arm64-mmu.c
> @@ -41,7 +41,7 @@ struct mm_region k3_mem_map[] = {
>  	}, {
>  		.virt = 0x500000000UL,
>  		.phys = 0x500000000UL,
> -		.size = 0x400000000UL,
> +		.size = 0x380000000UL,
>  		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
>  			 PTE_BLOCK_NON_SHARE |
>  			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
> -- 
> 2.40.0
> 

Thanks.

Reviewed-by: Nishanth Menon <nm at ti.com>

-- 
Regards,
Nishanth Menon
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