[PATCH v1] arm: dts: nuvoton: modify npcm8xx reset property
Jim Liu
jim.t90615 at gmail.com
Wed Jan 24 02:54:51 CET 2024
Change reset method from generic to reset driver
Signed-off-by: Jim Liu <JJLIU0 at nuvoton.com>
---
arch/arm/dts/nuvoton-common-npcm8xx.dtsi | 2 +
arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi | 71 ++++++++----------------
2 files changed, 24 insertions(+), 49 deletions(-)
diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
index 1694ef8849..db7517cc9b 100644
--- a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
+++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/nuvoton,npcm8xx-reset.h>
/ {
#address-cells = <2>;
@@ -152,6 +153,7 @@
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_APB5>;
clock-names = "clk_apb5";
+ resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_PSPI2>;
status = "disabled";
};
diff --git a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
index 4c6d5bed44..bc047d4b44 100644
--- a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
+++ b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
@@ -20,34 +20,7 @@
compatible = "nuvoton,npcm845-reset", "syscon",
"simple-mfd";
reg = <0x0 0xf0801000 0x0 0xC4>;
- rstc1: reset-controller1 {
- compatible = "syscon-reset";
- #reset-cells = <1>;
- regmap = <&rstc>;
- offset = <NPCM8XX_RESET_IPSRST1>;
- mask = <0xFFFFFFFF>;
- };
- rstc2: reset-controller2 {
- compatible = "syscon-reset";
- #reset-cells = <1>;
- regmap = <&rstc>;
- offset = <NPCM8XX_RESET_IPSRST2>;
- mask = <0xFFFFFFFF>;
- };
- rstc3: reset-controller3 {
- compatible = "syscon-reset";
- #reset-cells = <1>;
- regmap = <&rstc>;
- offset = <NPCM8XX_RESET_IPSRST3>;
- mask = <0xFFFFFFFF>;
- };
- rstc4: reset-controller4 {
- compatible = "syscon-reset";
- #reset-cells = <1>;
- regmap = <&rstc>;
- offset = <NPCM8XX_RESET_IPSRST4>;
- mask = <0xFFFFFFFF>;
- };
+ #reset-cells = <2>;
};
clk: clock-controller at f0801000 {
@@ -70,7 +43,7 @@
clock-names = "stmmaceth";
pinctrl-names = "default";
pinctrl-0 = <&rg1mdio_pins>;
- resets = <&rstc2 NPCM8XX_RESET_GMAC1>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_GMAC1>;
status = "disabled";
};
@@ -85,7 +58,7 @@
pinctrl-names = "default";
pinctrl-0 = <&rg2_pins
&rg2mdio_pins>;
- resets = <&rstc2 NPCM8XX_RESET_GMAC2>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_GMAC2>;
status = "disabled";
};
@@ -101,7 +74,7 @@
pinctrl-0 = <&r1_pins
&r1err_pins
&r1md_pins>;
- resets = <&rstc1 NPCM8XX_RESET_GMAC3>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_GMAC3>;
status = "disabled";
};
@@ -117,7 +90,7 @@
pinctrl-0 = <&r2_pins
&r2err_pins
&r2md_pins>;
- resets = <&rstc1 NPCM8XX_RESET_GMAC4>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_GMAC4>;
status = "disabled";
};
@@ -125,7 +98,7 @@
compatible = "nuvoton,npcm845-ehci";
reg = <0x0 0xf0828100 0x0 0x1000>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rstc2 NPCM8XX_RESET_USBH1>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_USBH1>;
status = "disabled";
};
@@ -133,21 +106,21 @@
compatible = "nuvoton,npcm845-ehci";
reg = <0x0 0xf082a100 0x0 0x1000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&rstc4 NPCM8XX_RESET_USBH2>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBH2>;
status = "disabled";
};
ohci1: usb at f0829000 {
compatible = "nuvoton,npcm845-ohci";
reg = <0x0 0xF0829000 0x0 0x1000>;
- resets = <&rstc2 NPCM8XX_RESET_USBH1>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_USBH1>;
status = "disabled";
};
ohci2: usb at f082b000 {
compatible = "nuvoton,npcm845-ohci";
reg = <0x0 0xF082B000 0x0 0x1000>;
- resets = <&rstc4 NPCM8XX_RESET_USBH2>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBH2>;
status = "disabled";
};
@@ -160,21 +133,21 @@
compatible = "nuvoton,npcm845-usb-phy";
#phy-cells = <1>;
reg = <1>;
- resets = <&rstc3 NPCM8XX_RESET_USBPHY1>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_USBPHY1>;
status = "disabled";
};
usbphy2: usbphy at 2 {
compatible = "nuvoton,npcm845-usb-phy";
#phy-cells = <1>;
reg = <2>;
- resets = <&rstc3 NPCM8XX_RESET_USBPHY2>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_USBPHY2>;
status = "disabled";
};
usbphy3: usbphy at 3 {
compatible = "nuvoton,npcm845-usb-phy";
#phy-cells = <1>;
reg = <3>;
- resets = <&rstc4 NPCM8XX_RESET_USBPHY3>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBPHY3>;
status = "disabled";
};
};
@@ -186,7 +159,7 @@
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
- resets = <&rstc3 NPCM8XX_RESET_UDC0>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC0>;
status = "disable";
};
@@ -197,7 +170,7 @@
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
- resets = <&rstc1 NPCM8XX_RESET_UDC1>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC1>;
status = "disable";
};
@@ -208,7 +181,7 @@
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
- resets = <&rstc1 NPCM8XX_RESET_UDC2>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC2>;
status = "disable";
};
@@ -219,7 +192,7 @@
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
- resets = <&rstc1 NPCM8XX_RESET_UDC3>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC3>;
status = "disable";
};
@@ -230,7 +203,7 @@
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
- resets = <&rstc1 NPCM8XX_RESET_UDC4>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC4>;
status = "disable";
};
@@ -241,7 +214,7 @@
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
- resets = <&rstc1 NPCM8XX_RESET_UDC5>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC5>;
status = "disable";
};
@@ -252,7 +225,7 @@
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
- resets = <&rstc1 NPCM8XX_RESET_UDC6>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC6>;
status = "disable";
};
@@ -263,7 +236,7 @@
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
- resets = <&rstc3 NPCM8XX_RESET_UDC7>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC7>;
status = "disable";
};
@@ -274,7 +247,7 @@
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
- resets = <&rstc3 NPCM8XX_RESET_UDC8>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC8>;
status = "disable";
};
@@ -285,7 +258,7 @@
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_SU>;
clock-names = "clk_usb_bridge";
- resets = <&rstc3 NPCM8XX_RESET_UDC9>;
+ resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC9>;
status = "disable";
};
--
2.25.1
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