[PATCH 1/3] rockchip: rk35xx: Remove use of eMMC DDR52 mode

[Jonas Karlman]

Hi Eugen,

On 2024-01-27 04:48, Eugen Hristev wrote:
> Hi Jonas,
> 
> 
> On 1/27/24 01:26, Jonas Karlman wrote:
>> Writing to eMMC using DDR52 mode does not work reliably or at all on
>> RK356x and RK3588 boards.
>>
> 
> 
> This is related to the old issue I encountered last year with mmc write?

Yes, I think it is.

I did some testing on RK3566/RK3568/RK3588S/RK3588 boards with different
eMMC modules with following result:

Read seem to work with all enabled modes:
RK3566: MMC legacy, MMC High Speed (26MHz), MMC High Speed (52MHz),
        MMC DDR52 (52MHz) and HS200 (200MHz)
RK3568/RK3588S/RK3588: all above + HS400 (200MHz) and HS400ES (200MHz)

However, write had issues with some of the modes:
MMC DDR52 (52MHz): all RK35xx
HS400/HS400ES: only on RK3568 after changing hs400_txclk_tapnum to 8

HS200 seem to be the most stable write speed that worked on all SoCs.

So, dropping MMC DDR52 (52MHz) and enable use of HS200 (200MHz) seem to
be the best option to get speedy and working read and write eMMC.

Regards,
Jonas

> 
> Thanks,
> Eugen
> 
>> Fix this by removing the mmc-ddr-1_8v prop from sdhci nodes.
>>
>> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
>> ---
>>  arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi   | 1 -
>>  arch/arm/dts/rk3566-quartz64-b-u-boot.dtsi   | 1 -
>>  arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi | 1 -
>>  arch/arm/dts/rk3566-soquartz-u-boot.dtsi     | 1 -
>>  arch/arm/dts/rk3568-lubancat-2-u-boot.dtsi   | 1 -
>>  arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi   | 1 -
>>  arch/arm/dts/rk3568-odroid-m1-u-boot.dtsi    | 1 -
>>  arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi    | 1 -
>>  arch/arm/dts/rk3568-rock-3a-u-boot.dtsi      | 1 -
>>  arch/arm/dts/rk3588-rock-5b-u-boot.dtsi      | 1 -
>>  arch/arm/dts/rk3588-turing-rk1-u-boot.dtsi   | 1 -
>>  arch/arm/dts/rk3588s-rock-5a-u-boot.dtsi     | 1 -
>>  12 files changed, 12 deletions(-)
>>

[snip]