[PATCH v2] arm: mach-k3: j721s2_init: Support less than max DDR controllers

[Neha Malcom Francis]

Hi all

On 30/01/24 15:12, Neha Malcom Francis wrote:
> The number of DDR controllers to be initialised and used should depend
> on the device tree with the constraint of the maximum number of
> controllers the device supports. Since J721S2 has multiple (2)
> controllers, instead of hardcoding the number of probes, move to
> depending on the device tree UCLASS_RAM nodes present.
> 
> Signed-off-by: Neha Malcom Francis <n-francis at ti.com>
> ---
> Changes since v1:
> https://lore.kernel.org/all/20240130074139.2627793-1-n-francis@ti.com/
> - Moved away from using loop since J721S2 has only two controllers
>    (Udit)
> 
> Boot logs:
> https://gist.github.com/nehamalcom/740e3dcc1e94ca36250f0248d73f6b37
> 
>   arch/arm/mach-k3/j721s2_init.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c
> index fb0708bae1..07f9221baf 100644
> --- a/arch/arm/mach-k3/j721s2_init.c
> +++ b/arch/arm/mach-k3/j721s2_init.c
> @@ -228,8 +228,8 @@ void k3_mem_init(void)
>   			panic("DRAM 0 init failed: %d\n", ret);
>   
>   		ret = uclass_next_device_err(&dev);
> -		if (ret)
> -			panic("DRAM 1 init failed: %d\n", ret);
> +		if (ret && ret != -ENODEV)
> +			panic("DRAM %d init failed: %d\n", ctr, ret);
>   	}
>   	spl_enable_cache();
>   }

Kindly ignore this patch, will resend v2.

-- 
Thanking You
Neha Malcom Francis