[PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node
E Shattow
lucent at gmail.com
Sun Jul 21 03:47:28 CEST 2024
Hi, I am testing on Milk-V Mars CM Lite, and I add to these devicetree
changes at runtime from board/starfive/visionfive2/spl.c
On Thu, Jul 18, 2024 at 6:38 PM Minda Chen <minda.chen at starfivetech.com> wrote:
>
> Add Jh7110 Cadence USB dts node, Visionfive2 default setting
> is USB 2.0 device.
>
> Signed-off-by: Minda Chen <minda.chen at starfivetech.com>
> ---
> .../dts/jh7110-starfive-visionfive-2.dtsi | 5 ++
> arch/riscv/dts/jh7110.dtsi | 52 +++++++++++++++++++
> 2 files changed, 57 insertions(+)
>
> diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> index e11babc1cd..44785bbee3 100644
> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> @@ -378,3 +378,8 @@
> };
> };
> };
> +
> +&usb_cdns3 {
> + dr_mode = "peripheral";
> + status = "okay";
> +};
> diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
> index 2cdc683d49..1eee924e1d 100644
> --- a/arch/riscv/dts/jh7110.dtsi
> +++ b/arch/riscv/dts/jh7110.dtsi
> @@ -371,6 +371,58 @@
> status = "disabled";
> };
>
> + usb0: usb at 10100000 {
> + compatible = "starfive,jh7110-usb";
> + ranges = <0x0 0x0 0x10100000 0x100000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + starfive,stg-syscon = <&stg_syscon 0x4>;
> + clocks = <&stgcrg JH7110_STGCLK_USB_LPM>,
> + <&stgcrg JH7110_STGCLK_USB_STB>,
> + <&stgcrg JH7110_STGCLK_USB_APB>,
> + <&stgcrg JH7110_STGCLK_USB_AXI>,
> + <&stgcrg JH7110_STGCLK_USB_UTMI_APB>;
> + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
> + resets = <&stgcrg JH7110_STGRST_USB_PWRUP>,
> + <&stgcrg JH7110_STGRST_USB_APB>,
> + <&stgcrg JH7110_STGRST_USB_AXI>,
> + <&stgcrg JH7110_STGRST_USB_UTMI_APB>;
> + reset-names = "pwrup", "apb", "axi", "utmi_apb";
> +
> + usb_cdns3: usb at 0 {
> + compatible = "cdns,usb3";
> + reg = <0x0 0x10000>,
> + <0x10000 0x10000>,
> + <0x20000 0x10000>;
> + reg-names = "otg", "xhci", "dev";
> + interrupts = <100>, <108>, <110>;
> + interrupt-names = "host", "peripheral", "otg";
> + phys = <&usbphy0>;
> + phy-names = "cdns3,usb2-phy";
> + };
> + };
> +
> + usbphy0: phy at 10200000 {
> + compatible = "starfive,jh7110-usb-phy";
> + reg = <0x0 0x10200000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
> + <&stgcrg JH7110_STGCLK_USB_APP_125>;
> + clock-names = "125m", "app_125m";
> + #phy-cells = <0>;
> + };
> +
> + pciephy0: phy at 10210000 {
> + compatible = "starfive,jh7110-pcie-phy";
> + reg = <0x0 0x10210000 0x0 0x10000>;
> + #phy-cells = <0>;
> + };
> +
> + pciephy1: phy at 10220000 {
> + compatible = "starfive,jh7110-pcie-phy";
> + reg = <0x0 0x10220000 0x0 0x10000>;
> + #phy-cells = <0>;
> + };
> +
> stgcrg: clock-controller at 10230000 {
> compatible = "starfive,jh7110-stgcrg";
> reg = <0x0 0x10230000 0x0 0x10000>;
> --
> 2.17.1
>
Access fault
starting USB...
Bus usb at 0: cdns-usb3-host usb at 0: set 1 has failed, back to 0
scanning bus usb at 0 for devices... Unhandled exception: Load access fault
EPC: 00000000fff85ce2 RA: 00000000fff85cdc TVAL: 0000000000000004
EPC: 0000000040246ce2 RA: 0000000040246cdc reloc adjusted
Code: 9863 3ee7 8526 f0ef c37f 651c 3a03 0105 (43dc)
resetting ...
when I add only these:
int offset;
offset = fdt_path_offset(fdt, "/soc/pinctrl at 13040000"); /* &sysgpio */
fdt_add_subnode(fdt, offset, "usb0-0");
fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),
"usb_pins", "/soc/pinctrl at 13040000/usb0-0");
offset = fdt_path_offset(fdt, "/soc/pinctrl at 13040000/usb0-0");
/* usb_pins */
fdt_create_phandle(fdt, offset);
fdt_add_subnode(fdt, offset, "driver-vbus-pin");
offset = fdt_path_offset(fdt,
"/soc/pinctrl at 13040000/usb0-0/driver-vbus-pin");
fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */
fdt_setprop_empty(fdt, offset, "bias-disable");
fdt_setprop_empty(fdt, offset, "input-disable");
fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
fdt_setprop_u32(fdt, offset, "slew-rate", 0);
offset = fdt_path_offset(fdt, "/soc/usb at 10100000"); /* &usb0 */
fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
fdt_setprop_u32(fdt, offset, "pinctrl-0", fdt_get_phandle(fdt,
fdt_path_offset(fdt, "/soc/pinctrl at 13040000/usb0-0")));
fdt_setprop_string(fdt, offset, "status", "okay");
offset = fdt_path_offset(fdt, "/soc/usb at 10100000/usb at 0"); /*
&usb_cdns3 */
fdt_setprop_string(fdt, offset, "dr_mode", "host");
Success USB is working but PCI disabled if instead I add all of this:
int offset;
offset = fdt_path_offset(fdt, "/soc/pinctrl at 13040000"); /* &sysgpio */
fdt_add_subnode(fdt, offset, "usb0-0");
fdt_setprop_string(fdt, fdt_path_offset(fdt, "/__symbols__"),
"usb_pins", "/soc/pinctrl at 13040000/usb0-0");
offset = fdt_path_offset(fdt, "/soc/pinctrl at 13040000/usb0-0");
/* usb_pins */
fdt_create_phandle(fdt, offset);
fdt_add_subnode(fdt, offset, "driver-vbus-pin");
offset = fdt_path_offset(fdt,
"/soc/pinctrl at 13040000/usb0-0/driver-vbus-pin");
fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */
fdt_setprop_empty(fdt, offset, "bias-disable");
fdt_setprop_empty(fdt, offset, "input-disable");
fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
fdt_setprop_u32(fdt, offset, "slew-rate", 0);
offset = fdt_path_offset(fdt, "/soc/pcie at 2b000000"); /* &pcie0 */
fdt_setprop_string(fdt, offset, "status", "disabled");
offset = fdt_path_offset(fdt, "/soc/phy at 10210000"); /* &pciephy0 */
fdt_setprop_u32(fdt, offset, "starfive,sys-syscon",
fdt_get_phandle(fdt, fdt_path_offset(fdt,
"/soc/sys_syscon at 13030000"))); /* = <&sys_syscon> */
fdt_appendprop_u32(fdt, offset, "starfive,sys-syscon", 0x18);
/* append <magic number> */
fdt_setprop_u32(fdt, offset, "starfive,stg-syscon",
fdt_get_phandle(fdt, fdt_path_offset(fdt,
"/soc/stg_syscon at 10240000"))); /* = <&stg_syscon> */
fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x148);
/* append <magic number> */
fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x1f4);
/* append <magic number> */
fdt_setprop_string(fdt, offset, "status", "okay");
offset = fdt_path_offset(fdt, "/soc/usb at 10100000"); /* &usb0 */
fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
fdt_setprop_u32(fdt, offset, "pinctrl-0", fdt_get_phandle(fdt,
fdt_path_offset(fdt, "/soc/pinctrl at 13040000/usb0-0")));
fdt_setprop_string(fdt, offset, "status", "okay");
offset = fdt_path_offset(fdt, "/soc/usb at 10100000/usb at 0"); /*
&usb_cdns3 */
fdt_setprop_u32(fdt, offset, "phys",
fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/phy at 10200000"))); /* =
<&usbphy0> */
fdt_appendprop_u32(fdt, offset, "phys",
fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/phy at 10210000"))); /*
append <&pciephy0> */
fdt_setprop(fdt, offset, "phy-names",
"cdns3,usb2-phy\0cdns3,usb3-phy",
sizeof("cdns3,usb2-phy\0cdns3,usb3-phy"));
fdt_setprop_string(fdt, offset, "dr_mode", "host");
I have made some mistake for devicetree and USB2.0 with keeping pcie0
(not disable)? or is there a problem with the implementation?
Best regards, -E Shattow
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