[PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node
Minda Chen
minda.chen at starfivetech.com
Tue Jul 23 12:16:12 CEST 2024
>
> On Mon, Jul 22, 2024 at 6:29 PM Minda Chen <minda.chen at starfivetech.com>
> wrote:
> >
> >
> >
> > >
> > > On Sat, Jul 20, 2024 at 6:47 PM E Shattow <lucent at gmail.com> wrote:
> > > >
> > > > Hi, I am testing on Milk-V Mars CM Lite, and I add to these
> > > > devicetree changes at runtime from
> > > > board/starfive/visionfive2/spl.c
> > > >
> > > > On Thu, Jul 18, 2024 at 6:38 PM Minda Chen
> > > > <minda.chen at starfivetech.com>
> > > wrote:
> > > > >
> > > > > Add Jh7110 Cadence USB dts node, Visionfive2 default setting is
> > > > > USB
> > > > > 2.0 device.
> > > > >
> > > > > Signed-off-by: Minda Chen <minda.chen at starfivetech.com>
> > > > > ---
> > > > > .../dts/jh7110-starfive-visionfive-2.dtsi | 5 ++
> > > > > arch/riscv/dts/jh7110.dtsi | 52
> > > +++++++++++++++++++
> > > > > 2 files changed, 57 insertions(+)
> > > > >
> > > > > diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > index e11babc1cd..44785bbee3 100644
> > > > > --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > @@ -378,3 +378,8 @@
> > > > > };
> > > > > };
> > > > > };
> > > > > +
> > > > > +&usb_cdns3 {
> > > > > + dr_mode = "peripheral";
> > > > > + status = "okay";
> > > > > +};
> > > > > diff --git a/arch/riscv/dts/jh7110.dtsi
> > > > > b/arch/riscv/dts/jh7110.dtsi index 2cdc683d49..1eee924e1d 100644
> > > > > --- a/arch/riscv/dts/jh7110.dtsi
> > > > > +++ b/arch/riscv/dts/jh7110.dtsi
> > > > > @@ -371,6 +371,58 @@
> > > > > status = "disabled";
> > > > > };
> > > > >
> > > > > + usb0: usb at 10100000 {
> > > > > + compatible = "starfive,jh7110-usb";
> > > > > + ranges = <0x0 0x0 0x10100000 0x100000>;
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <1>;
> > > > > + starfive,stg-syscon = <&stg_syscon 0x4>;
> > > > > + clocks = <&stgcrg
> > > JH7110_STGCLK_USB_LPM>,
> > > > > + <&stgcrg
> > > JH7110_STGCLK_USB_STB>,
> > > > > + <&stgcrg
> > > JH7110_STGCLK_USB_APB>,
> > > > > + <&stgcrg
> > > JH7110_STGCLK_USB_AXI>,
> > > > > + <&stgcrg
> > > JH7110_STGCLK_USB_UTMI_APB>;
> > > > > + clock-names = "lpm", "stb", "apb",
> > > > > + "axi",
> > > "utmi_apb";
> > > > > + resets = <&stgcrg
> > > JH7110_STGRST_USB_PWRUP>,
> > > > > + <&stgcrg
> > > JH7110_STGRST_USB_APB>,
> > > > > + <&stgcrg
> > > JH7110_STGRST_USB_AXI>,
> > > > > + <&stgcrg
> > > JH7110_STGRST_USB_UTMI_APB>;
> > > > > + reset-names = "pwrup", "apb", "axi",
> > > > > + "utmi_apb";
> > > > > +
> > > > > + usb_cdns3: usb at 0 {
> > > > > + compatible = "cdns,usb3";
> > > > > + reg = <0x0 0x10000>,
> > > > > + <0x10000 0x10000>,
> > > > > + <0x20000 0x10000>;
> > > > > + reg-names = "otg", "xhci",
> "dev";
> > > > > + interrupts = <100>, <108>,
> <110>;
> > > > > + interrupt-names = "host",
> > > "peripheral", "otg";
> > > > > + phys = <&usbphy0>;
> > > > > + phy-names = "cdns3,usb2-phy";
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + usbphy0: phy at 10200000 {
> > > > > + compatible = "starfive,jh7110-usb-phy";
> > > > > + reg = <0x0 0x10200000 0x0 0x10000>;
> > > > > + clocks = <&syscrg
> > > JH7110_SYSCLK_USB_125M>,
> > > > > + <&stgcrg
> > > JH7110_STGCLK_USB_APP_125>;
> > > > > + clock-names = "125m", "app_125m";
> > > > > + #phy-cells = <0>;
> > > > > + };
> > > > > +
> > > > > + pciephy0: phy at 10210000 {
> > > > > + compatible = "starfive,jh7110-pcie-phy";
> > > > > + reg = <0x0 0x10210000 0x0 0x10000>;
> > > > > + #phy-cells = <0>;
> > > > > + };
> > > > > +
> > > > > + pciephy1: phy at 10220000 {
> > > > > + compatible = "starfive,jh7110-pcie-phy";
> > > > > + reg = <0x0 0x10220000 0x0 0x10000>;
> > > > > + #phy-cells = <0>;
> > > > > + };
> > > > > +
> > > > > stgcrg: clock-controller at 10230000 {
> > > > > compatible = "starfive,jh7110-stgcrg";
> > > > > reg = <0x0 0x10230000 0x0 0x10000>;
> > > > > --
> > > > > 2.17.1
> > > > >
> > > >
> > > > Access fault
> > > >
> > > > starting USB...
> > > > Bus usb at 0: cdns-usb3-host usb at 0: set 1 has failed, back to 0
> > > > scanning bus usb at 0 for devices... Unhandled exception:
> > > > Load
> > > access fault
> > > > EPC: 00000000fff85ce2 RA: 00000000fff85cdc TVAL:
> > > 0000000000000004
> > > > EPC: 0000000040246ce2 RA: 0000000040246cdc reloc adjusted
> > > >
> > > > Code: 9863 3ee7 8526 f0ef c37f 651c 3a03 0105 (43dc)
> > > >
> > > >
> > > > resetting ...
> > > >
> > > > when I add only these:
> > > >
> > > > int offset;
> > > >
> > > > offset = fdt_path_offset(fdt, "/soc/pinctrl at 13040000"); /*
> > > &sysgpio */
> > > > fdt_add_subnode(fdt, offset, "usb0-0");
> > > > fdt_setprop_string(fdt, fdt_path_offset(fdt,
> > > > "/__symbols__"), "usb_pins", "/soc/pinctrl at 13040000/usb0-0");
> > > > offset = fdt_path_offset(fdt,
> > > > "/soc/pinctrl at 13040000/usb0-0");
> > > > /* usb_pins */
> > > > fdt_create_phandle(fdt, offset);
> > > > fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> > > > offset = fdt_path_offset(fdt,
> > > > "/soc/pinctrl at 13040000/usb0-0/driver-vbus-pin");
> > > > fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
> > > > GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE,
> GPI_NONE)
> > > */
> > > > fdt_setprop_empty(fdt, offset, "bias-disable");
> > > > fdt_setprop_empty(fdt, offset, "input-disable");
> > > > fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> > > > fdt_setprop_u32(fdt, offset, "slew-rate", 0);
> > > >
> > > > offset = fdt_path_offset(fdt, "/soc/usb at 10100000"); /* &usb0
> */
> > > > fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> > > > fdt_setprop_u32(fdt, offset, "pinctrl-0",
> > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> "/soc/pinctrl at 13040000/usb0-0")));
> > > > fdt_setprop_string(fdt, offset, "status", "okay");
> > > >
> > > > offset = fdt_path_offset(fdt, "/soc/usb at 10100000/usb at 0");
> > > > /*
> > > > &usb_cdns3 */
> > > > fdt_setprop_string(fdt, offset, "dr_mode", "host");
> > > >
> > > > Success USB is working but PCI disabled if instead I add all of this:
> > > >
>
> > I checked t Milk-V CM board do not contain USB3.0 host So I think the
> > USB 3.0 configuration is not required.
>
> I agree it should be USB 2.0, but with your patch this is the only configuration
> that does anything successful with USB2.0 or 3.0
>
>
> >
> > > > int offset;
> > > >
> > > > offset = fdt_path_offset(fdt, "/soc/pinctrl at 13040000"); /*
> > > &sysgpio */
> > > > fdt_add_subnode(fdt, offset, "usb0-0");
> > > > fdt_setprop_string(fdt, fdt_path_offset(fdt,
> > > > "/__symbols__"), "usb_pins", "/soc/pinctrl at 13040000/usb0-0");
> > > > offset = fdt_path_offset(fdt,
> > > > "/soc/pinctrl at 13040000/usb0-0");
> > > > /* usb_pins */
> > > > fdt_create_phandle(fdt, offset);
> > > > fdt_add_subnode(fdt, offset, "driver-vbus-pin");
> > > > offset = fdt_path_offset(fdt,
> > > > "/soc/pinctrl at 13040000/usb0-0/driver-vbus-pin");
> > > > fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /*
> > > > GPIOMUX(25, GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE,
> GPI_NONE)
> > > */
> > > > fdt_setprop_empty(fdt, offset, "bias-disable");
> > > > fdt_setprop_empty(fdt, offset, "input-disable");
> > > > fdt_setprop_empty(fdt, offset, "input-schmitt-disable");
> > > > fdt_setprop_u32(fdt, offset, "slew-rate", 0);
> > > >
> > > > offset = fdt_path_offset(fdt, "/soc/pcie at 2b000000"); /* &pcie0
> */
> > > > fdt_setprop_string(fdt, offset, "status", "disabled");
> > > >
> > > > offset = fdt_path_offset(fdt, "/soc/phy at 10210000"); /*
> > > > &pciephy0
> > > */
> > > > fdt_setprop_u32(fdt, offset, "starfive,sys-syscon",
> > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > > "/soc/sys_syscon at 13030000"))); /* = <&sys_syscon> */
> > > > fdt_appendprop_u32(fdt, offset, "starfive,sys-syscon",
> > > > 0x18);
> > > > /* append <magic number> */
> > > > fdt_setprop_u32(fdt, offset, "starfive,stg-syscon",
> > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> > > > "/soc/stg_syscon at 10240000"))); /* = <&stg_syscon> */
> > > > fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon",
> > > > 0x148);
> > > > /* append <magic number> */
> > > > fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon",
> > > > 0x1f4);
> > > > /* append <magic number> */
> > > > fdt_setprop_string(fdt, offset, "status", "okay");
> > > >
> > > > offset = fdt_path_offset(fdt, "/soc/usb at 10100000"); /* &usb0
> */
> > > > fdt_setprop_string(fdt, offset, "pinctrl-names", "default");
> > > > fdt_setprop_u32(fdt, offset, "pinctrl-0",
> > > > fdt_get_phandle(fdt, fdt_path_offset(fdt,
> "/soc/pinctrl at 13040000/usb0-0")));
> > > > fdt_setprop_string(fdt, offset, "status", "okay");
> > > >
> > > > offset = fdt_path_offset(fdt, "/soc/usb at 10100000/usb at 0");
> > > > /*
> > > > &usb_cdns3 */
> > > > fdt_setprop_u32(fdt, offset, "phys",
> > > > fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/phy at 10200000")));
> > > > /* = <&usbphy0> */
> > > > fdt_appendprop_u32(fdt, offset, "phys",
> > > > fdt_get_phandle(fdt, fdt_path_offset(fdt, "/soc/phy at 10210000"))); /*
> append <&pciephy0> */
> > > > fdt_setprop(fdt, offset, "phy-names",
> > > > "cdns3,usb2-phy\0cdns3,usb3-phy",
> > > > sizeof("cdns3,usb2-phy\0cdns3,usb3-phy"));
> > > > fdt_setprop_string(fdt, offset, "dr_mode", "host");
> > > >
> > > > I have made some mistake for devicetree and USB2.0 with keeping
> > > > pcie0 (not disable)? or is there a problem with the implementation?
> > > >
> > > > Best regards, -E Shattow
> > >
>
> > I don’t have a Milk-V CM board. So I just can test this code to Star64.
> > Thanks. I will test this and add the code to board_fixup_star64().
>
> Can you try to configure in USB2.0-only mode on Star64? Do you see the same
> problem with "load access fault"?
>
Yes ，USB 2.0 only can work.
> ...snip...
>
> Same devicetree fixup code but separated some of the statements to multiple
> lines:
>
> https://paste.debian.net/1324036/
>
> ```
Now I can see the issue,Usb 2.0 host can work in Milk-V CM, but PCIe can not work.
Is that correct?
The PCIe in CM board is PCIe0， The PCIe1 is not used. So I think
disable PCIe1 node and just set USB 2.0 to host is OK.
milkV CM PCIe0 setting is the same with VisionFive v2.
The USB 3.0 setting should not be added.
This USB 3.0 setting. Should NOT be added to Milk-V CM board.
&pciephy0 {
starfive,sys-syscon = <&sys_syscon 0x18>;
starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
status = "okay";
};
&usb_cdns3 {
phys = <&usbphy0>, <&pciephy0>;
phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
dr_mode = "host";
status = "okay";
};
> diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
> index b794b73b6b..b4b0930e75 100644
> --- a/board/starfive/visionfive2/spl.c
> +++ b/board/starfive/visionfive2/spl.c
> @@ -123,6 +123,53 @@ static const struct starfive_vf2_pro star64_pine64[] = {
> "tx-internal-delay-ps", "300"},
> };
>
> +void spl_fdt_fixup_jh7110_cadence_usb3_host(void *fdt) { int offset;
> + u32 phandle;
> +
> + offset = fdt_path_offset(fdt, "/soc/pinctrl at 13040000"); /* &sysgpio */
> + fdt_add_subnode(fdt, offset, "usb0-0"); fdt_setprop_string(fdt,
> + fdt_path_offset(fdt, "/__symbols__"),
> "usb_pins", "/soc/pinctrl at 13040000/usb0-0");
> + offset = fdt_path_offset(fdt, "/soc/pinctrl at 13040000/usb0-0"); /*
> + usb_pins */ fdt_create_phandle(fdt, offset); fdt_add_subnode(fdt,
> + offset, "driver-vbus-pin"); offset = fdt_path_offset(fdt,
> + "/soc/pinctrl at 13040000/usb0-0/driver-vbus-pin");
> + fdt_setprop_u32(fdt, offset, "pinmux", 0xff070019); /* GPIOMUX(25,
> GPOUT_SYS_USB_DRIVE_VBUS, GPOEN_ENABLE, GPI_NONE) */
> + fdt_setprop_empty(fdt, offset, "bias-disable"); fdt_setprop_empty(fdt,
> + offset, "input-disable"); fdt_setprop_empty(fdt, offset,
> + "input-schmitt-disable"); fdt_setprop_u32(fdt, offset, "slew-rate",
> + 0);
> +
> + offset = fdt_path_offset(fdt, "/soc/pcie at 2b000000"); /* &pcie0 */
> + fdt_setprop_string(fdt, offset, "status", "disabled");
> +
> + offset = fdt_path_offset(fdt, "/soc/phy at 10210000"); /* &pciephy0 */
> + phandle = fdt_get_phandle(fdt, fdt_path_offset(fdt,
> "/soc/sys_syscon at 13030000")); /* = <&sys_syscon> */
> + fdt_setprop_u32(fdt, offset, "starfive,sys-syscon", phandle);
> + fdt_appendprop_u32(fdt, offset, "starfive,sys-syscon", 0x18); /*
> append <magic number> */
> + phandle = fdt_get_phandle(fdt, fdt_path_offset(fdt,
> "/soc/stg_syscon at 10240000")); /* = <&stg_syscon> */
> + fdt_setprop_u32(fdt, offset, "starfive,stg-syscon", phandle);
> + fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x148); /*
> append <magic number> */
> + fdt_appendprop_u32(fdt, offset, "starfive,stg-syscon", 0x1f4); /*
> append <magic number> */
> + fdt_setprop_string(fdt, offset, "status", "okay");
> +
> + offset = fdt_path_offset(fdt, "/soc/usb at 10100000"); /* &usb0 */
> + fdt_setprop_string(fdt, offset, "pinctrl-names", "default"); phandle =
> + fdt_get_phandle(fdt, fdt_path_offset(fdt,
> "/soc/pinctrl at 13040000/usb0-0")); /* <&usb_pins> */
> + fdt_setprop_u32(fdt, offset, "pinctrl-0", phandle);
> + fdt_setprop_string(fdt, offset, "status", "okay");
> +
> + offset = fdt_path_offset(fdt, "/soc/usb at 10100000/usb at 0"); /*
> + &usb_cdns3 */ phandle = fdt_get_phandle(fdt, fdt_path_offset(fdt,
> "/soc/phy at 10200000")); /* = <&usbphy0> */
> + fdt_setprop_u32(fdt, offset, "phys", phandle); phandle =
> + fdt_get_phandle(fdt, fdt_path_offset(fdt,
> "/soc/phy at 10210000")); /* append <&pciephy0> */
> + fdt_appendprop_u32(fdt, offset, "phys", phandle);
> +fdt_setprop_string(fdt, offset, "phy-names", "cdns3,usb2-phy");
> +fdt_appendprop_string(fdt, offset, "phy-names", "cdns3,usb3-phy");
> +fdt_setprop_string(fdt, offset, "dr_mode", "host"); }
> +
> void spl_fdt_fixup_mars(void *fdt)
> {
> static const char compat[] = "milkv,mars\0starfive,jh7110"; @@ -335,6
> +382,8 @@ void spl_fdt_fixup_star64(void *fdt)
> break;
> }
> }
> +
> + spl_fdt_fixup_jh7110_cadence_usb3_host(fdt);
> }
>
> void spl_perform_fixups(struct spl_image_info *spl_image) ```
>
> I think there is missing some of the USB2.0-only logic in your patch.
> Can you try some more testing to understand why this fault happens here?
>
> Thanks,
>
> -E
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