[PATCH 1/2] imx8mm-cl-iot-gate: Add support for Samsung 4GB DDR

[Fabio Estevam]

From: Fabio Estevam <festevam at denx.de>

Newer versions of the imx8mm-cl-iot-gate boards may come populated with a
Samsung 4GB DDR model.

Add support for it.

Signed-off-by: Fabio Estevam <festevam at denx.de>
---
 board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
index b230478b611a..f1048a1ab2ab 100644
--- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
+++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
@@ -47,7 +47,9 @@ struct lpddr4_desc {
 static const struct lpddr4_desc lpddr4_array[] = {
 	{ .name = "Nanya",	.id = 0x05000010, .subind = 0xff,
 	  .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
-	{ .name = "Samsung",	.id = 0x01061010, .subind = 0xff,
+	{ .name = "Samsung",	.id = 0x01061010, .subind = 0x04,
+	  .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
+	{ .name = "Samsung",	.id = 0x01061010, .subind = 0x02,
 	  .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
 	{ .name = "Kingston",	.id = 0xff000010, .subind = 0x04,
 	  .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
-- 
2.34.1