[PATCH 3/3] board: rockchip: Fix panel detection for mainline A-TF

[Chris Morgan]

From: Chris Morgan <macromorgan at hotmail.com>

The current panel detection logic crashes when the device boots with
mainline A-TF, causing a reboot loop. It turns out mainline A-TF
doesn't enable the VO power domain like the BSP A-TF did.

Set the VO domain on and use a memory barrier to ensure it is powered
up before we attempt to do the panel detection.

Signed-off-by: Chris Morgan <macromorgan at hotmail.com>
---
 board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c | 13 +++++++++++++
 configs/anbernic-rgxx3-rk3566_defconfig    |  2 --
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
index c1d1826fd14..f4e7c1ab360 100644
--- a/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
+++ b/board/anbernic/rgxx3_rk3566/rgxx3-rk3566.c
@@ -22,6 +22,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define PMU_BASE_ADDR		0xfdd90000
+#define PMU_PWR_GATE_SFTCON	0xa0
+#define PMU_PD_VO_DWN_ENA	BIT(7)
+
 #define GPIO0_BASE		0xfdd60000
 #define GPIO4_BASE		0xfe770000
 #define GPIO_SWPORT_DR_L	0x0000
@@ -311,6 +315,15 @@ int rgxx3_detect_display(void)
 	int i;
 	u8 panel_id[2];
 
+	/* Disable VO power domain power-down */
+	writel((PMU_PD_VO_DWN_ENA << 16),
+	       PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);
+	/*
+	 * System will crash if the power domain isn't enabled before
+	 * we start trying to talk to the DSI panel.
+	 */
+	wmb();
+
 	/*
 	 * Take panel out of reset status.
 	 * Set GPIO4_A0 to output.
diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig
index f5e5470df8c..49d3766613e 100644
--- a/configs/anbernic-rgxx3-rk3566_defconfig
+++ b/configs/anbernic-rgxx3-rk3566_defconfig
@@ -49,8 +49,6 @@ CONFIG_SPL_REGMAP=y
 CONFIG_SPL_SYSCON=y
 CONFIG_SPL_ADC=y
 CONFIG_SPL_CLK=y
-CONFIG_ARM_SMCCC_FEATURES=y
-CONFIG_SCMI_FIRMWARE=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MISC=y
-- 
2.34.1