[PATCH v14 0/8] spi-nor: Add parallel and stacked memories support

[Tom Rini]

On Thu, Sep 26, 2024 at 10:25:00AM +0530, Venkatesh Yadav Abbarapu wrote:

> This series adds support for Xilinx qspi parallel and
> stacked memeories.
> 
> In parallel mode, the current implementation assumes that a maximum
> of two flashes are connected. The QSPI controller splits the data
> evenly between both the flashes so, both the flashes that are connected
> in parallel mode should be identical.
> During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in
> nor->flags.
> 
> In stacked mode the current implementation assumes that a maximum of two
> flashes are connected and both the flashes are of same make but can differ
> in sizes. So, except the sizes all other flash parameters of both the flashes
> are identical.
> 
> Spi-nor will pass on the appropriate flash select flag to low level driver,
> and it will select pass all the data to that particular flash.
> 
> Write operation in parallel mode are performed in page size * 2 chunks as
> each write operation results in writing both the flashes. For doubling the
> address space each operation is performed at addr/2 flash offset, where addr
> is the address specified by the user.
> 
> Similarly for read and erase operations it will read from both flashes, so
> size and offset are divided by 2 and send to flash.

Size-wise, this seems OK. There might be room for a little improvement
in the "we don't need this" case, but it can be left for later, if it's
really possible to tweak it more and it's an issue down the line. I
intend to grab this for next in about a week, unless there's further
feedback.

-- 
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 659 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20240926/2124e1f4/attachment.sig>