[PATCH 2/7] clk/qcom: apq8096: fix set rate for the uart clock

[neil.armstrong at linaro.org]

On 07/04/2025 10:19, Jorge Ramirez-Ortiz wrote:
> The function should return a valid rate.
> 
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez at oss.qualcomm.com>
> ---
>   drivers/clk/qcom/clock-apq8096.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
> index c77d69128b0..bc00826a5e8 100644
> --- a/drivers/clk/qcom/clock-apq8096.c
> +++ b/drivers/clk/qcom/clock-apq8096.c
> @@ -87,7 +87,8 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
>   		return clk_init_sdc(priv, rate);
>   		break;
>   	case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/
> -		return clk_init_uart(priv);
> +		clk_init_uart(priv);
> +		return 7372800;
>   	default:
>   		return 0;
>   	}

Reviewed-by: Neil Armstrong <neil.armstrong at linaro.org>