[PATCH v2 03/30] arm64: dts: rockchip: Add UART clocks for RK3528 SoC

[Kever Yang]

On 2025/4/8 06:46, Jonas Karlman wrote:
> From: Yao Zi <ziyao at disroot.org>
>
> Add missing clocks in UART nodes for RK3528 SoC.
>
> Signed-off-by: Yao Zi <ziyao at disroot.org>
> Link: https://lore.kernel.org/r/20250217061142.38480-10-ziyao@disroot.org
> Signed-off-by: Heiko Stuebner <heiko at sntech.de>
>
> [ upstream commit: b9454434d0349223418f74fbfa7b902104da9bc5 ]
>
> (cherry picked from commit 12f69f638472dc9cf1b62816c7d4407de1846d12)
> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
>   dts/upstream/src/arm64/rockchip/rk3528.dtsi | 17 ++++++++++++++++-
>   1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> index 37fd40377076..5b334690356a 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> +++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> @@ -168,7 +168,8 @@
>   		uart0: serial at ff9f0000 {
>   			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
>   			reg = <0x0 0xff9f0000 0x0 0x100>;
> -			clock-frequency = <24000000>;
> +			clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
> +			clock-names = "baudclk", "apb_pclk";
>   			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
>   			reg-io-width = <4>;
>   			reg-shift = <2>;
> @@ -178,6 +179,8 @@
>   		uart1: serial at ff9f8000 {
>   			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
>   			reg = <0x0 0xff9f8000 0x0 0x100>;
> +			clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
> +			clock-names = "baudclk", "apb_pclk";
>   			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>   			reg-io-width = <4>;
>   			reg-shift = <2>;
> @@ -187,6 +190,8 @@
>   		uart2: serial at ffa00000 {
>   			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
>   			reg = <0x0 0xffa00000 0x0 0x100>;
> +			clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
> +			clock-names = "baudclk", "apb_pclk";
>   			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
>   			reg-io-width = <4>;
>   			reg-shift = <2>;
> @@ -195,6 +200,8 @@
>   
>   		uart3: serial at ffa08000 {
>   			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> +			clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
> +			clock-names = "baudclk", "apb_pclk";
>   			reg = <0x0 0xffa08000 0x0 0x100>;
>   			reg-io-width = <4>;
>   			reg-shift = <2>;
> @@ -204,6 +211,8 @@
>   		uart4: serial at ffa10000 {
>   			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
>   			reg = <0x0 0xffa10000 0x0 0x100>;
> +			clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
> +			clock-names = "baudclk", "apb_pclk";
>   			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
>   			reg-io-width = <4>;
>   			reg-shift = <2>;
> @@ -213,6 +222,8 @@
>   		uart5: serial at ffa18000 {
>   			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
>   			reg = <0x0 0xffa18000 0x0 0x100>;
> +			clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
> +			clock-names = "baudclk", "apb_pclk";
>   			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
>   			reg-io-width = <4>;
>   			reg-shift = <2>;
> @@ -222,6 +233,8 @@
>   		uart6: serial at ffa20000 {
>   			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
>   			reg = <0x0 0xffa20000 0x0 0x100>;
> +			clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
> +			clock-names = "baudclk", "apb_pclk";
>   			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
>   			reg-io-width = <4>;
>   			reg-shift = <2>;
> @@ -231,6 +244,8 @@
>   		uart7: serial at ffa28000 {
>   			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
>   			reg = <0x0 0xffa28000 0x0 0x100>;
> +			clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
> +			clock-names = "baudclk", "apb_pclk";
>   			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
>   			reg-io-width = <4>;
>   			reg-shift = <2>;