[PATCH v2 22/30] mmc: rockchip_sdhci: Gate clock for glitch free phase switching

[Kever Yang]

On 2025/4/8 06:46, Jonas Karlman wrote:
> Enable clock stopping to gate clock during phase code change to ensure
> glitch free phase switching in auto-tuning circuit. Fixes HS200 mode
> on RK3528.
>
> POST_CHANGE_DLY
> Time taken for phase switching and stable clock output.
> - Less than 4-cycle latency
>
> PRE_CHANGE_DLY
> Maximum Latency specification between transmit clock and receive clock.
> - Less than 4-cycle latency
>
> TUNE_CLK_STOP_EN
> Clock stopping control for Tuning and auto-tuning circuit. When enabled,
> clock gate control output is pulled low before changing phase select
> codes. This effectively stops the receive clock. Changing phase code
> when clocks are stopped ensures glitch free phase switching.
> - Clocks stopped during phase code change
>
> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
> v2: No change
> ---
>   drivers/mmc/rockchip_sdhci.c | 9 +++++++++
>   1 file changed, 9 insertions(+)
>
> diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
> index 2c54b8a942da..c0f986784366 100644
> --- a/drivers/mmc/rockchip_sdhci.c
> +++ b/drivers/mmc/rockchip_sdhci.c
> @@ -50,6 +50,10 @@
>   #define DWCMSHC_EMMC_EMMC_CTRL		0x52c
>   #define DWCMSHC_CARD_IS_EMMC		BIT(0)
>   #define DWCMSHC_ENHANCED_STROBE		BIT(8)
> +#define DWCMSHC_EMMC_AT_CTRL		0x540
> +#define EMMC_AT_CTRL_TUNE_CLK_STOP_EN	BIT(16)
> +#define EMMC_AT_CTRL_PRE_CHANGE_DLY	17
> +#define EMMC_AT_CTRL_POST_CHANGE_DLY	19
>   #define DWCMSHC_EMMC_DLL_CTRL		0x800
>   #define DWCMSHC_EMMC_DLL_CTRL_RESET	BIT(1)
>   #define DWCMSHC_EMMC_DLL_RXCLK		0x804
> @@ -326,6 +330,11 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab
>   		udelay(1);
>   		sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
>   
> +		extra = 0x3 << EMMC_AT_CTRL_POST_CHANGE_DLY |
> +			0x3 << EMMC_AT_CTRL_PRE_CHANGE_DLY |
> +			EMMC_AT_CTRL_TUNE_CLK_STOP_EN;
> +		sdhci_writel(host, extra, DWCMSHC_EMMC_AT_CTRL);
> +
>   		/* Init DLL settings */
>   		extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
>   			DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC |