[PATCH v4 4/4] board/BuR/zynq: initial commit
Michal Simek
michal.simek at amd.com
Mon Apr 14 08:48:40 CEST 2025
On 4/4/25 09:28, Bernhard Messerklinger wrote:
> This commit adds support for the brcp1, brsmarc2, brcp150 and brcp170
> boards. This boards are based on the Xilinx Zynq SoC.
>
> Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger at br-automation.com>
> ---
>
> Changes in v4:
> - Fix device tree Makefile to only build B&R Zynq device trees
> if the target is from B&R.
>
> Changes in v3:
> - Split spi_flash and qspi controller node in device tree for the usage
> of bootph-all
> - Merge binman descriptions into one zynq-binman-brcp1
> - Add links instead of manually including u-boot.dtsi files
> - Remove empty MAC addresses nodes from the device tree
> - Seperate B&R Zynq device trees in the devicetree Makefile
>
> Changes in v2:
> - Remove all unnecessary device-tree entries
> - Reviewed led names (no pattern restriction found)
> - Fix maintainers file
> - Cleanup of code
> - Move preboot variable to env file
>
> arch/arm/dts/Makefile | 7 +
> arch/arm/dts/zynq-binman-brcp1.dtsi | 102 +++++++
> arch/arm/dts/zynq-brcp1.dtsi | 131 +++++++++
> arch/arm/dts/zynq-brcp150-u-boot.dtsi | 34 +++
> arch/arm/dts/zynq-brcp150.dts | 173 +++++++++++
> arch/arm/dts/zynq-brcp170-u-boot.dtsi | 26 ++
> arch/arm/dts/zynq-brcp170.dts | 139 +++++++++
> arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi | 30 ++
> arch/arm/dts/zynq-brcp1_1r.dts | 28 ++
> arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi | 1 +
> arch/arm/dts/zynq-brcp1_1r_switch.dts | 30 ++
> arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi | 1 +
> arch/arm/dts/zynq-brcp1_2r.dts | 21 ++
> arch/arm/dts/zynq-brsmarc2-u-boot.dtsi | 30 ++
> arch/arm/dts/zynq-brsmarc2.dts | 157 ++++++++++
> arch/arm/mach-zynq/Kconfig | 1 +
> board/BuR/zynq/Kconfig | 14 +
> board/BuR/zynq/MAINTAINERS | 11 +
> board/BuR/zynq/Makefile | 15 +
> board/BuR/zynq/brcp150/board.c | 4 +
> board/BuR/zynq/brcp150/ps7_init_gpl.c | 278 ++++++++++++++++++
> board/BuR/zynq/brcp170/board.c | 4 +
> board/BuR/zynq/brcp170/ps7_init_gpl.c | 274 +++++++++++++++++
> board/BuR/zynq/brcp1_1r/board.c | 4 +
> board/BuR/zynq/brcp1_1r/ps7_init_gpl.c | 274 +++++++++++++++++
> board/BuR/zynq/brcp1_1r_switch/board.c | 4 +
> board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c | 270 +++++++++++++++++
> board/BuR/zynq/brcp1_2r/board.c | 4 +
> board/BuR/zynq/brcp1_2r/ps7_init_gpl.c | 277 +++++++++++++++++
> board/BuR/zynq/brsmarc2/board.c | 30 ++
> board/BuR/zynq/brsmarc2/ps7_init_gpl.c | 276 +++++++++++++++++
> board/BuR/zynq/common/board.c | 231 +++++++++++++++
> board/BuR/zynq/env/brcp1.env | 109 +++++++
> board/BuR/zynq/env/brcp150.env | 119 ++++++++
> configs/brcp150_defconfig | 121 ++++++++
> configs/brcp170_defconfig | 120 ++++++++
> configs/brcp1_1r_defconfig | 120 ++++++++
> configs/brcp1_1r_switch_defconfig | 121 ++++++++
> configs/brcp1_2r_defconfig | 120 ++++++++
> configs/brsmarc2_defconfig | 120 ++++++++
> include/configs/brzynq.h | 21 ++
> 41 files changed, 3852 insertions(+)
> create mode 100644 arch/arm/dts/zynq-binman-brcp1.dtsi
> create mode 100644 arch/arm/dts/zynq-brcp1.dtsi
> create mode 100644 arch/arm/dts/zynq-brcp150-u-boot.dtsi
> create mode 100644 arch/arm/dts/zynq-brcp150.dts
> create mode 100644 arch/arm/dts/zynq-brcp170-u-boot.dtsi
> create mode 100644 arch/arm/dts/zynq-brcp170.dts
> create mode 100644 arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi
> create mode 100644 arch/arm/dts/zynq-brcp1_1r.dts
> create mode 120000 arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi
> create mode 100644 arch/arm/dts/zynq-brcp1_1r_switch.dts
> create mode 120000 arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi
> create mode 100644 arch/arm/dts/zynq-brcp1_2r.dts
> create mode 100644 arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
> create mode 100644 arch/arm/dts/zynq-brsmarc2.dts
> create mode 100644 board/BuR/zynq/Kconfig
> create mode 100644 board/BuR/zynq/MAINTAINERS
> create mode 100644 board/BuR/zynq/Makefile
> create mode 100644 board/BuR/zynq/brcp150/board.c
> create mode 100644 board/BuR/zynq/brcp150/ps7_init_gpl.c
> create mode 100644 board/BuR/zynq/brcp170/board.c
> create mode 100644 board/BuR/zynq/brcp170/ps7_init_gpl.c
> create mode 100644 board/BuR/zynq/brcp1_1r/board.c
> create mode 100644 board/BuR/zynq/brcp1_1r/ps7_init_gpl.c
> create mode 100644 board/BuR/zynq/brcp1_1r_switch/board.c
> create mode 100644 board/BuR/zynq/brcp1_1r_switch/ps7_init_gpl.c
> create mode 100644 board/BuR/zynq/brcp1_2r/board.c
> create mode 100644 board/BuR/zynq/brcp1_2r/ps7_init_gpl.c
> create mode 100644 board/BuR/zynq/brsmarc2/board.c
> create mode 100644 board/BuR/zynq/brsmarc2/ps7_init_gpl.c
> create mode 100644 board/BuR/zynq/common/board.c
> create mode 100644 board/BuR/zynq/env/brcp1.env
> create mode 100644 board/BuR/zynq/env/brcp150.env
> create mode 100644 configs/brcp150_defconfig
> create mode 100644 configs/brcp170_defconfig
> create mode 100644 configs/brcp1_1r_defconfig
> create mode 100644 configs/brcp1_1r_switch_defconfig
> create mode 100644 configs/brcp1_2r_defconfig
> create mode 100644 configs/brsmarc2_defconfig
> create mode 100644 include/configs/brzynq.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 267b0179a5f..10c1e34713a 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -297,6 +297,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
> zynqmp-zc1751-xm017-dc3.dtb \
> zynqmp-zc1751-xm018-dc4.dtb \
> zynqmp-zc1751-xm019-dc5.dtb
> +dtb-$(CONFIG_TARGET_ZYNQ_BR) += \
> + zynq-brcp1_2r.dtb \
> + zynq-brcp1_1r.dtb \
> + zynq-brcp1_1r_switch.dtb \
> + zynq-brsmarc2.dtb \
> + zynq-brcp150.dtb \
> + zynq-brcp170.dtb
>
> zynqmp-p-a2197-00-revA-x-prc-01-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo
> zynqmp-p-a2197-00-revA-x-prc-02-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo
> diff --git a/arch/arm/dts/zynq-binman-brcp1.dtsi b/arch/arm/dts/zynq-binman-brcp1.dtsi
> new file mode 100644
> index 00000000000..3cc8ee8b810
> --- /dev/null
> +++ b/arch/arm/dts/zynq-binman-brcp1.dtsi
> @@ -0,0 +1,102 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2025 B&R Industrial Automation GmbH
> + */
> +
> + #include <config.h>
> +
> +/ {
> + binman {
> + bootph-all;
> + filename = "flash.bin";
> + pad-byte = <0xff>;
> + align-size = <16>;
> + align = <16>;
> +
> + blob at 0 {
> + filename = "spl/boot.bin";
> + offset = <0x0>;
> + };
> +
> + fit {
> + description = "U-Boot BR Zynq boards";
> + offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
> +
> + images {
> + uboot {
> + description = "U-Boot BR Zynq";
> + type = "firmware";
> + os = "u-boot";
> + arch = "arm";
> + compression = "none";
> + load = <CONFIG_TEXT_BASE>;
> + u-boot-nodtb {
> + };
> + };
> +
> + fdt-0 {
> + description = "DTB BR Zynq";
> + type = "flat_dt";
> + arch = "arm";
> + compression = "none";
> + u-boot-dtb {
> + };
> + };
> + };
> +
> + configurations {
> + default = "conf-0";
> +
> + conf-0 {
> + description = "BR Zynq";
> + firmware = "uboot";
> + fdt = "fdt-0";
> + };
> + };
> + };
> +
> + blob-ext at 0 {
> + filename = "blobs/cfg.img";
> + offset = <0xC0000>;
> + size = <0x10000>;
> + optional;
> + };
> +
> + blob-ext at 5 {
> + filename = "blobs/cfg_opt.img";
> + offset = <0xD0000>;
> + size = <0x10000>;
> + optional;
> + };
> +
> + blob-ext at 1 {
> + bootph-all;
> + filename = "blobs/bitstream.bit";
> + offset = <0x100000>;
> + size = <0x200000>;
> + optional;
> + };
> +
> + blob-ext at 4 {
> + bootph-all;
> + filename = "blobs/bitstream_update.bit";
> + offset = <0x400000>;
> + size = <0x200000>;
> + optional;
> + };
> +
> + blob-ext at 2 {
> + filename = "blobs/bootar.itb";
> + offset = <0x900000>;
> + size = <0x600000>;
> + optional;
> + };
> +
> + blob-ext at 3 {
> + filename = "blobs/dtb.bin";
> + offset = <0xF00000>;
> + size = <0x100000>;
> + optional;
> + };
> + };
> +};
> diff --git a/arch/arm/dts/zynq-brcp1.dtsi b/arch/arm/dts/zynq-brcp1.dtsi
> new file mode 100644
> index 00000000000..ebaf42d9419
> --- /dev/null
> +++ b/arch/arm/dts/zynq-brcp1.dtsi
> @@ -0,0 +1,131 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 B&R Industrial Automation GmbH
> + */
> +
> +/include/ "zynq-7000.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "BRCP1 CPU";
> + compatible = "br,cp1",
> + "xlnx,zynq-7000";
> +
> + aliases {
> + i2c0 = &i2c0;
> + serial0 = &uart0;
> + spi0 = &qspi;
> + mmc0 = &sdhci0;
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0x0 0x40000000>;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + usb_phy0: phy0 {
> + compatible = "usb-nop-xceiv";
> + #phy-cells = <0>;
> + };
> +
> + brd_rst: board_reset {
> + compatible = "br,board-reset";
> + pin = <&gpio0 9 GPIO_ACTIVE_HIGH>;
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + se_green {
> + label = "S_E_GREEN";
> + gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>;
> + default-state = "off";
> + };
> + se_red {
> + label = "S_E_RED";
> + gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
> + default-state = "off";
> + };
> + rdy_f_yellow {
> + label = "RDY_F_YELLOW";
> + gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>;
> + default-state = "off";
> + };
> + re_green {
> + label = "R_E_GREEN";
> + gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>;
> + default-state = "off";
> + };
> + re_red {
> + label = "R_E_RED";
> + gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> + plk_se_green {
> + label = "PLK_S_E_GREEN";
> + gpios = <&ledgpio 5 GPIO_ACTIVE_LOW>;
> + default-state = "off";
> + };
> + eth_se_green {
> + label = "ETH_S_E_GREEN";
> + gpios = <&ledgpio 6 GPIO_ACTIVE_LOW>;
> + default-state = "off";
> + };
> + };
> +};
> +
> +&i2c0 {
> + status = "okay";
> + clock-frequency = <100000>;
> +
> + ledgpio: max7320 at 5d { /* board LED */
> + status = "okay";
> + compatible = "maxim,max7320";
> + reg = <0x5d>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + ngpios = <8>;
> + };
> +
> + pmic0: da9062 at 58 {
> + compatible = "dlg,da9062";
> + reg = <0x58>;
> + };
> +};
> +
> +&sdhci0 {
> + status = "okay";
> + max-frequency = <25000000>;
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&qspi {
> + status = "okay";
> + spi-max-frequency = <100000000>;
> +
> + spi_flash: spiflash at 0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
> + spi-max-frequency = <100000000>;
> + spi-cpol;
> + spi-cpha;
> + reg = <0>;
> + };
> +};
> +
> +&usb0 {
> + status = "okay";
> + dr_mode = "host";
> + usb-phy = <&usb_phy0>;
> +};
> +
> +&gpio0 {
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/zynq-brcp150-u-boot.dtsi b/arch/arm/dts/zynq-brcp150-u-boot.dtsi
> new file mode 100644
> index 00000000000..1bfd5f27a7e
> --- /dev/null
> +++ b/arch/arm/dts/zynq-brcp150-u-boot.dtsi
> @@ -0,0 +1,34 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 B&R Industrial Automation GmbH
> + */
> +
> +#include "zynq-binman-brcp1.dtsi"
> +
> +&i2c0 {
> + bootph-all;
> +};
> +
> +&uart0 {
> + bootph-all;
> +};
> +
> +&qspi {
> + bootph-all;
> +};
> +
> +&spi_flash {
> + bootph-all;
> +};
> +
> +&gpio0 {
> + bootph-all;
> +};
> +
> +&brd_rst {
> + bootph-all;
> +};
> +
> +&rs232_en {
> + bootph-all;
> +};
nit:
All these nodes with bootph-all don't need to be here.
The reason was that flags (especially previous one) were not the part of
dt-schema. But now it is that's why there is no reason to separate them in
special file. You can simply add them to zynq-brcp150.dtsi
Visible also with some other files below.
Anyway I don't have issue with this patch that's why feel free to add
Acked-by: Michal Simek <michal.simek at amd.com>
Thanks,
Michal
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