[PATCH v2 01/16] rockchip: sdram: honor CFG_SYS_SDRAM_BASE when defining ram regions

[Jonas Karlman]

Hi Heiko,

On 2025-04-14 22:00, Heiko Stuebner wrote:
> Currently the sdram code for arm64 expects CFG_SYS_SDRAM_BASE to be 0.
> The ram being in front and the device-area behind it.
> 
> The upcoming RK3576 uses a different layout, with the device area
> in front the ram, which then also extends past the 4G mark.
> 
> Adapt both the generic zone definitions as well as the ATAG parser
> to be usable on devices where CFG_SYS_SDRAM_BASE is not 0.
> 
> Signed-off-by: Heiko Stuebner <heiko at sntech.de>
> Reviewed-by: Jonas Karlman <jonas at kwiboo.se>
> Reviewed-by: Quentin Schulz <quentin.schulz at cherry.de>
> ---
>  arch/arm/mach-rockchip/sdram.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
> index aa3f47c3f20..f6d9c503bfd 100644
> --- a/arch/arm/mach-rockchip/sdram.c
> +++ b/arch/arm/mach-rockchip/sdram.c
> @@ -182,9 +182,9 @@ static int rockchip_dram_init_banksize(void)
>  		 * BL31 (TF-A) reserves the first 2MB but DDR_MEM tag may not
>  		 * have it, so force this space as reserved.
>  		 */
> -		if (start_addr < SZ_2M) {
> -			size -= SZ_2M - start_addr;
> -			start_addr = SZ_2M;
> +		if (start_addr < SZ_2M + CFG_SYS_SDRAM_BASE) {

A small nitpick for consistency:

	if (start_addr < CFG_SYS_SDRAM_BASE + SZ_2M) {

That would result in 4x grep-able "CFG_SYS_SDRAM_BASE + SZ_2M" in this
file.

Regards,
Jonas

> +			size -= CFG_SYS_SDRAM_BASE + SZ_2M - start_addr;
> +			start_addr = CFG_SYS_SDRAM_BASE + SZ_2M;
>  		}
>  
>  		/*
> @@ -229,7 +229,7 @@ static int rockchip_dram_init_banksize(void)
>  					return -EINVAL;
>  				}
>  
> -				size -= rsrv_end - start_addr;
> +				size -= rsrv_end - (start_addr - CFG_SYS_SDRAM_BASE);
>  				start_addr = rsrv_end;
>  				break;
>  			}
> @@ -302,8 +302,8 @@ int dram_init_banksize(void)
>  	debug("Couldn't use ATAG (%d) to detect DDR layout, falling back...\n",
>  	      ret);
>  
> -	/* Reserve 0x200000 for ATF bl31 */
> -	gd->bd->bi_dram[0].start = 0x200000;
> +	/* Reserve 2M for ATF bl31 */
> +	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M;
>  	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
>  
>  	/* Add usable memory beyond the blob of space for peripheral near 4GB */