[PATCH] xilinx: versal-net: Enable loading bitstreams via fpga

[Michal Simek]

On 4/10/25 10:22, Michal Simek wrote:
> Enable FPGA Xilinx interface and driver for loading bistreams.
> 
> Signed-off-by: Michal Simek <michal.simek at amd.com>
> ---
> 
>   configs/xilinx_versal_net_virt_defconfig | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig
> index 49dc9bb5c4d3..add233d2dbb7 100644
> --- a/configs/xilinx_versal_net_virt_defconfig
> +++ b/configs/xilinx_versal_net_virt_defconfig
> @@ -76,6 +76,8 @@ CONFIG_DFU_RAM=y
>   CONFIG_FPGA_XILINX=y
>   CONFIG_FPGA_VERSALPL=y
>   CONFIG_ARM_FFA_TRANSPORT=y
> +CONFIG_FPGA_XILINX=y
> +CONFIG_FPGA_VERSALPL=y
>   CONFIG_ZYNQ_GPIO=y
>   CONFIG_DM_I2C=y
>   CONFIG_SYS_I2C_CADENCE=y


Applied.
M