[PATCH v1 0/5] Agilex5 DDR Driver Enhancement

[tingting.meng at altera.com]

From: Tingting Meng <tingting.meng at altera.com>

This patch series enhances the U-Boot DDR driver for Agilex 5 with
improvements in memory handling, cache control, and ECC support. The
updates include:
	1. MMU mapping regions were added for the second and third DDR
	   memory banks.
	2. LMB_ARCH_MEM_MAP is enabled to correctly handle memory
	   reservations for the second and third DDR memory banks.
	3. Cache allocation for dirty writes in the CCU system cache was
	   disabled for performance optimization.
	4. In-line ECC support was added for LPDDR by reserving the last
	   one-eighth of the memory space for ECC data. Full memory
	   initialization using the BIST MEM INIT mailbox command, based
	   on address and size, is required to correctly generate ECC data
	   and enable proper ECC logic verification.
	5. ECC debug information was enhanced to improve the readability
	   of error messages.

This patch series has been tested on the Agilex 5 devkit with RAM boot
using TFTP and the ARM DS debugger.

Tingting Meng (5):
  arm: socfpga: agilex5: Add MMU mapping region
  arm: socfpga: socfpga_soc64: Enable LMB_ARCH_MEM_MAP
  arm: dts: agilex5: Update CCU configuration
  ddr: altera: agilex5: LPDDRs in-line ECC support
  ddr: altera: iossm: Enhance debug information for ECC errors

 arch/arm/Kconfig                              |   1 +
 arch/arm/dts/socfpga_agilex5-u-boot.dtsi      |   6 +-
 .../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi |  26 +-
 arch/arm/mach-socfpga/board.c                 |  13 +
 arch/arm/mach-socfpga/mmu-arm64_s10.c         |  14 ++
 drivers/ddr/altera/iossm_mailbox.c            | 225 ++++++++++++++++--
 drivers/ddr/altera/iossm_mailbox.h            |  11 +-
 drivers/ddr/altera/sdram_agilex5.c            |  19 +-
 drivers/ddr/altera/sdram_soc64.c              |  52 ++--
 9 files changed, 303 insertions(+), 64 deletions(-)

-- 
2.25.1