[PATCH v3 12/15] arm64: dts: rockchip: add rk3576 otp node

[Kever Yang]

On 2025/4/16 05:51, Heiko Stuebner wrote:
> This adds the otp node to the rk3576 soc devicetree including the
> individual fields we know about.
>
> Tested-by: Nicolas Frattaroli <nicolas.frattaroli at collabora.com>
> Signed-off-by: Heiko Stuebner <heiko at sntech.de>
> Link: https://lore.kernel.org/r/20250210224510.1194963-7-heiko@sntech.de

Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
>
> [ upstream commit: 8715d2eeb062f6859c252bb6c87b363230b66e9f ]
>
> (cherry picked from commit d67cf6de8aacb4abcdfb516eeb8a511a4a657bc1)
> ---
>   dts/upstream/src/arm64/rockchip/rk3576.dtsi | 39 +++++++++++++++++++++
>   1 file changed, 39 insertions(+)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3576.dtsi b/dts/upstream/src/arm64/rockchip/rk3576.dtsi
> index 4dde954043e..29b47799849 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3576.dtsi
> +++ b/dts/upstream/src/arm64/rockchip/rk3576.dtsi
> @@ -1260,6 +1260,45 @@
>   			status = "disabled";
>   		};
>   
> +		otp: otp at 2a580000 {
> +			compatible = "rockchip,rk3576-otp";
> +			reg = <0x0 0x2a580000 0x0 0x400>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
> +				 <&cru CLK_OTP_PHY_G>;
> +			clock-names = "otp", "apb_pclk", "phy";
> +			resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>;
> +			reset-names = "otp", "apb";
> +
> +			/* Data cells */
> +			cpu_code: cpu-code at 2 {
> +				reg = <0x02 0x2>;
> +			};
> +			otp_cpu_version: cpu-version at 5 {
> +				reg = <0x05 0x1>;
> +				bits = <3 3>;
> +			};
> +			otp_id: id at a {
> +				reg = <0x0a 0x10>;
> +			};
> +			cpub_leakage: cpub-leakage at 1e {
> +				reg = <0x1e 0x1>;
> +			};
> +			cpul_leakage: cpul-leakage at 1f {
> +				reg = <0x1f 0x1>;
> +			};
> +			npu_leakage: npu-leakage at 20 {
> +				reg = <0x20 0x1>;
> +			};
> +			gpu_leakage: gpu-leakage at 21 {
> +				reg = <0x21 0x1>;
> +			};
> +			log_leakage: log-leakage at 22 {
> +				reg = <0x22 0x1>;
> +			};
> +		};
> +
>   		gic: interrupt-controller at 2a701000 {
>   			compatible = "arm,gic-400";
>   			reg = <0x0 0x2a701000 0 0x10000>,