[PATCH] net: gem: ignore tx_clk if MII is used

[Martin Kaistra]

Hi Harini,

Am 22.04.25 um 18:17 schrieb Katakam, Harini:
> [AMD Official Use Only - AMD Internal Distribution Only]
> 
> Hi Martin
> 
>> -----Original Message-----
>> From: U-Boot <u-boot-bounces at lists.denx.de> On Behalf Of Martin Kaistra
>> Sent: Tuesday, April 15, 2025 8:34 PM
>> To: u-boot at lists.denx.de
>> Cc: joe.hershberger at ni.com; rfried.dev at gmail.com; Simek, Michal
>> <michal.simek at amd.com>
>> Subject: [PATCH] net: gem: ignore tx_clk if MII is used
>>
>> If the MII interface is used, the PHY is the clock master, thus don't set the clock
> 
> Can you please describe your HW configuration?

on my HW the PS GEM is connected to a MII-to-RMII converter which is then 
connected via RMII to the PHY.

The linux driver (drivers/net/ethernet/cadence/macb_main.c) has a similar 
exception for MII mode in macb_set_tx_clk().

Thanks,
Martin

> Based on the spec,
> 1. In 10/100 GMII mode, tx_clk will run at either 2.5 MHz or 25 MHz as
> determined by the external PHY MII clock input.
> 2. When using gigabit mode, the transmit clock must be sourced from a
> 125 MHz reference clock.
> 3. In RMII mode, tx_clk should be connected to the rmii_tx_clk outputs.
> In both cases 2 and 3, the MAC is the clock master.
> 
> If you are using a HW connection such as Zynq:
> PS GEM - GMII to RGMII/SGMII shim - External PHY,
> then the I understand that you'll get such an error message and that should
> be removed. But I'm not sure if this applies to MII type.
> 
> Regards,
> Harini
> 
>> rate. On Zynq-7000, this will prevent the following
>> error:
>>    zynq_gem ethernet at e000b000: failed to set tx clock rate 25000000
>>
>> Signed-off-by: Martin Kaistra <martin.kaistra at linutronix.de>
>> ---
>>   drivers/net/zynq_gem.c | 14 ++++++++------
>>   1 file changed, 8 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index
>> 461805ae53f..703e22479d2 100644
>> --- a/drivers/net/zynq_gem.c
>> +++ b/drivers/net/zynq_gem.c
>> @@ -567,12 +567,14 @@ static int zynq_gem_init(struct udevice *dev)
>>        }
>>   #endif
>>
>> -     ret = clk_get_rate(&priv->tx_clk);
>> -     if (ret != clk_rate) {
>> -             ret = clk_set_rate(&priv->tx_clk, clk_rate);
>> -             if (IS_ERR_VALUE(ret)) {
>> -                     dev_err(dev, "failed to set tx clock rate %ld\n", clk_rate);
>> -                     return ret;
>> +     if (priv->interface != PHY_INTERFACE_MODE_MII) {
>> +             ret = clk_get_rate(&priv->tx_clk);
>> +             if (ret != clk_rate) {
>> +                     ret = clk_set_rate(&priv->tx_clk, clk_rate);
>> +                     if (IS_ERR_VALUE(ret)) {
>> +                             dev_err(dev, "failed to set tx clock rate %ld\n",
>> clk_rate);
>> +                             return ret;
>> +                     }
>>                }
>>        }
>>
>> --
>> 2.39.5
>