[PATCH] video: mxsfb: fix pixel clock polarity

[Sam Meredith]

DISPLAY_FLAGS_PIXDATA_NEGEDGE means the controller drives the data on
pixel clocks falling edge. That is DOTCLK_POL=0 (default) not 1.

Signed-off-by: Sam Meredith<sam at aandtinstruments.com>
---

This patch was submitted back in 2021 but never merged. I arrived at the exact same patch.
https://marc.info/?l=u-boot&m=163794537017364&w=2

As was pointed out back then, the mxsfb-drm driver in the Linux kernel has
made the same change and it remains to this day:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mxsfb?h=v5.16-rc2&id=53990e416bb7adaa59d045f325a47f31a11b75ee <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/gpu/drm/mxsfb?h=v5.16-rc2&id=53990e416bb7adaa59d045f325a47f31a11b75ee>

I found this was required on an IMX8X SoM.
Without the patch a splash screen displays with aliasing-like jagged edges.

  drivers/video/mxsfb.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index e72839cead4..58338ed6004 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -159,7 +159,7 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
          vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
      if(flags & DISPLAY_FLAGS_VSYNC_HIGH)
          vdctrl0 |= LCDIF_VDCTRL0_VSYNC_POL;
-    if(flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+    if(flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
          vdctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL;
      if(flags & DISPLAY_FLAGS_DE_HIGH)
          vdctrl0 |= LCDIF_VDCTRL0_ENABLE_POL;