回复: [PATCH v1 1/4] ehci-mx6: Add powerup_fixup implementation

[Alice Guo (OSS)]

> -----邮件原件-----
> 发件人: Marek Vasut <marek.vasut at mailbox.org>
> 发送时间: 2025年11月30日 9:05
> 收件人: Alice Guo (OSS) <alice.guo at oss.nxp.com>; u-boot at lists.denx.de;
> dl-uboot-imx <uboot-imx at nxp.com>
> 抄送: Marek Vasut <marex at denx.de>; Marek Vasut
> <marek.vasut+renesas at mailbox.org>; Tom Rini <trini at konsulko.com>; Ye Li
> <ye.li at nxp.com>; Fabio Estevam <festevam at gmail.com>;
> tharvey at gateworks.com; Mattijs Korpershoek <mkorpershoek at kernel.org>;
> Patrice Chotard <patrice.chotard at foss.st.com>; Stefano Babic
> <sbabic at nabladev.com>; Peng Fan <peng.fan at nxp.com>; Lukasz Majewski
> <lukma at denx.de>; Simon Glass <sjg at chromium.org>; David Zang
> <davidzangcs at gmail.com>; Alice Guo <alice.guo at nxp.com>
> 主题: Re: [PATCH v1 1/4] ehci-mx6: Add powerup_fixup implementation
> 
> On 11/28/25 2:16 PM, alice.guo at oss.nxp.com wrote:
> > From: Ye Li <ye.li at nxp.com>
> >
> > When doing port reset, the PR bit of PORTSC1 will be automatically
> > cleared by our IP, but standard EHCI needs explicit clear by software.
> > The EHCI-HCD driver follow the EHCI specification, so after 50ms wait,
> > it clear the PR bit by writting to the PORTSC1 register with value
> > loaded before setting PR.
> >
> > This sequence is ok for our IP when the delay time is exact. But when
> > the timer is slower
> 
> How can the timer be slower ? Maybe there is some bug somewhere else ?

On i.MX8ULP, the A35 system counter uses the internal LPO. The trimmed frequency of the LPO is not as accurate as an external oscillator.

Best regards,
Alice Guo