[PATCH v4] SDRAM Calibration Failed fix for GEN5 SoCFPGA

[Sune Brian]

Chee, Tien Fong <tienfong.chee at altera.com> 於 2025年11月28日週五 下午6:17寫道：
>
> Hi Brian,
>
> On 28/11/2025 6:04 am, Sune Brian wrote:
> > [CAUTION: This email is from outside your organization. Unless you trust the sender, do not click on links or open attachments as it may be a fraudulent email attempting to steal your information and/or compromise your computer.]
> >
> > Hi all
> >
> >>> CMD_CYCLIC is enabled by default ("default y") if its dependencies are
> >>> met (that is "CYCLIC" as specified by "depends on CYCLIC" in
> >>> cmd/Kconfig). So when you enable CONFIG_CYCLIC via menuconfig, it
> >>> enables (by default) CMD_CYCLIC as well. But you can disable it if you
> >>> don't need it for example. If you add a "select OPTION" in an option in
> >>> Kconfig, you cannot disable OPTION anymore.
> >>>
> >>> CMD_CYCLIC is not required, so you shouldn't "depends on" or "select" it.
> >> Yes this patch had removed it by cross-check via real board on the fail
> >> calibration issue. But CYCLIC and CYCLIC_SPL still a must to fix the issue.
> >>
> >> Brian
> > Would Altera also confirm this issue a bit?
> > I can repeat this issue by a fresh pull build.
>
> Thanks for sharing your findings. However, based on the behavior you
> described, I’m not fully convinced that enabling cyclic/watchdog is
> actually fixing the SDRAM calibration issue itself. From the SPL side,
> there is no clear timeout or calibration control path that would
> logically be corrected by turning on the cyclic framework, so the
> improvement may simply be due to timing shifts rather than a real fix.
>
> Before we go deeper into upstream work, could you try testing against
> the official Altera downstream tree?
>
> Altera official U-Boot (SoCFPGA):
> https://github.com/altera-fpga/u-boot-socfpga - branch socfpga_v2025.07
>
> This branch includes several Gen5 DDR related fixes that are not
> upstreamed yet. If calibration becomes stable with the downstream tree,
> then it is very likely that the real fix already exists there, and we
> can identify which patch addresses the root cause instead of spending
> time reverse engineering a solution that may already be solved.
>
> If the calibration still fails even on the official release, then at
> least we can rule out downstream fixes and focus efforts on the correct
> upstream location.
>
> Let me know the results, it will help us pinpoint whether the issue is
> timing-related or missing a specific patch.
>
> Thanks.
>
> Tien Fong
>

Hi T.F.

I am enclosing a bit log here.
I had diff both sequencer on mainstream and altera trunk.
No diff.

As for the sdram_gen5.c there are diff but no major point
before calibration fail is trigger. ECC is not use or setup.

Setup:
No CYCLIC no WDT all off on dts and .config.
No modification on code.
The below logs are trigger via reset key.

Pass case:
U-Boot SPL 2026.01-rc3-00043-gd5276409c0a1-dirty (Dec 01 2025 - 21:10:15 +0800)
sequencer: Preparing to start memory calibration
sdram_calibration_full:3939
run_mem_calibrate:3671
phy_mgr_initialize:115
rw_mgr_mem_initialize:1048
delay_for_n_mem_clocks:809: clocks=250 ... start
delay_for_n_mem_clocks:872 clocks=250 ... end
delay_for_n_mem_clocks:809: clocks=4 ... start
delay_for_n_mem_clocks:872 clocks=4 ... end
delay_for_n_mem_clocks:809: clocks=4 ... start
delay_for_n_mem_clocks:872 clocks=4 ... end
delay_for_n_mem_clocks:809: clocks=512 ... start
delay_for_n_mem_clocks:872 clocks=512 ... end
mem_calibrate:3492
mem_init_latency:3358
rw_mgr_mem_calibrate_vfifo:2853: 0 0
rw_mgr_mem_calibrate_read_load_patterns:1446
rw_mgr_mem_calibrate_dqs_enable_calibration:2747 (0,0)
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1959 0
rw_mgr_mem_calibrate_vfifo_center:2565: 0 0rw_mgr_mem_calibrate_writes:3295 0 0
rw_mgr_mem_calibrate_writes_center:3146 0
0rw_mgr_mem_calibrate_vfifo_end:2950 0
0rw_mgr_mem_calibrate_vfifo_center:2565: 0
0rw_mgr_mem_calibrate_vfifo:2853: 1 0
rw_mgr_mem_calibrate_read_load_patterns:1446
rw_mgr_mem_calibrate_dqs_enable_calibration:2747 (1,0)
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1959 1
rw_mgr_mem_calibrate_vfifo_center:2565: 1 0rw_mgr_mem_calibrate_writes:3295 1 8
rw_mgr_mem_calibrate_writes_center:3146 1
8rw_mgr_mem_calibrate_vfifo_end:2950 1
0rw_mgr_mem_calibrate_vfifo_center:2565: 1
0rw_mgr_mem_calibrate_vfifo:2853: 2 0
rw_mgr_mem_calibrate_read_load_patterns:1446
rw_mgr_mem_calibrate_dqs_enable_calibration:2747 (2,0)
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1959 2
rw_mgr_mem_calibrate_vfifo_center:2565: 2 0rw_mgr_mem_calibrate_writes:3295 2 16
rw_mgr_mem_calibrate_writes_center:3146 2
16rw_mgr_mem_calibrate_vfifo_end:2950 2
0rw_mgr_mem_calibrate_vfifo_center:2565: 2
0rw_mgr_mem_calibrate_vfifo:2853: 3 0
rw_mgr_mem_calibrate_read_load_patterns:1446
rw_mgr_mem_calibrate_dqs_enable_calibration:2747 (3,0)
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1959 3
rw_mgr_mem_calibrate_vfifo_center:2565: 3 0rw_mgr_mem_calibrate_writes:3295 3 24
rw_mgr_mem_calibrate_writes_center:3146 3
24rw_mgr_mem_calibrate_vfifo_end:2950 3
0rw_mgr_mem_calibrate_vfifo_center:2565: 3
0rw_mgr_mem_calibrate_lfifo:2979
rw_mgr_mem_calibrate_read_load_patterns:1446
delay_for_n_mem_clocks:809: clocks=4 ... start
delay_for_n_mem_clocks:872 clocks=4 ... end
delay_for_n_mem_clocks:809: clocks=4 ... start
delay_for_n_mem_clocks:872 clocks=4 ... end
sequencer: CALIBRATION PASSED
sequencer: Calibration complete
Trying to boot from MMC1

Fail case:
U-Boot SPL 2026.01-rc3-00043-gd5276409c0a1-dirty (Dec 01 2025 - 21:10:15 +0800)
sequencer: Preparing to start memory calibration
sdram_calibration_full:3939
run_mem_calibrate:3671
phy_mgr_initialize:115
rw_mgr_mem_initialize:1048
delay_for_n_mem_clocks:809: clocks=250 ... start
delay_for_n_mem_clocks:872 clocks=250 ... end
delay_for_n_mem_clocks:809: clocks=4 ... start
delay_for_n_mem_clocks:872 clocks=4 ... end
delay_for_n_mem_clocks:809: clocks=4 ... start
delay_for_n_mem_clocks:872 clocks=4 ... end
delay_for_n_mem_clocks:809: clocks=512 ... start
delay_for_n_mem_clocks:872 clocks=512 ... end
mem_calibrate:3492
mem_init_latency:3358
rw_mgr_mem_calibrate_vfifo:2853: 0 0
rw_mgr_mem_calibrate_read_load_patterns:1446
rw_mgr_mem_calibrate_dqs_enable_calibration:2747 (0,0)
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1959 0
rw_mgr_mem_calibrate_read_load_patterns:1446
rw_mgr_mem_calibrate_dqs_enable_calibration:2747 (0,0)
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1959 0
rw_mgr_mem_calibrate_read_load_patterns:1446
rw_mgr_mem_calibrate_dqs_enable_calibration:2747 (0,0)
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1959 0
rw_mgr_mem_calibrate_read_load_patterns:1446
rw_mgr_mem_calibrate_dqs_enable_calibration:2747 (0,0)
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1959 0
rw_mgr_mem_calibrate_read_load_patterns:1446
rw_mgr_mem_calibrate_dqs_enable_calibration:2747 (0,0)
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1959 0
delay_for_n_mem_clocks:809: clocks=4 ... start
delay_for_n_mem_clocks:872 clocks=4 ... end
delay_for_n_mem_clocks:809: clocks=4 ... start
delay_for_n_mem_clocks:872 clocks=4 ... end
sequencer: CALIBRATION FAILED
sequencer: Calibration complete
SDRAM calibration failed.
### ERROR ### Please RESET the board ###

Thanks,
Brian