[PATCH v2 2/2] imx8ulp_evk: Switch to use devicetree imported from Linux kernel release
alice.guo at oss.nxp.com
alice.guo at oss.nxp.com
Wed Dec 3 09:51:41 CET 2025
From: Alice Guo <alice.guo at nxp.com>
Enable OF_UPSTREAM for i.MX8ULP EVK so that devicetree imported from
Linux kernel release can be used.
If mailbox at 29220000 is enabled, gd->arch.ele_dev will be set to this
device for communication with ELE firmware. This is incorrect because
mu at 27020000 is the MU used for communication with the ELE firmware. To
prevent misconfiguration, disable mailbox at 29220000.
The driver model for watchdog timer is not enabled yet, so disable wdog3
temporarily.
Signed-off-by: Alice Guo <alice.guo at nxp.com>
---
arch/arm/dts/Makefile | 3 -
arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 8 +
arch/arm/dts/imx8ulp-evk.dts | 125 ---------
arch/arm/dts/imx8ulp.dtsi | 476 -----------------------------------
arch/arm/mach-imx/imx8ulp/Kconfig | 1 +
configs/imx8ulp_evk_defconfig | 2 +-
6 files changed, 10 insertions(+), 605 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 865ceb65f9a..b7ece30d1a3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -880,9 +880,6 @@ dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qxp-mek.dtb \
imx8-capricorn-cxg3.dtb \
-dtb-$(CONFIG_ARCH_IMX8ULP) += \
- imx8ulp-evk.dtb
-
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-data-modul-edm-sbc.dtb \
imx8mm-icore-mx8mm-ctouch2.dtb \
diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
index 2782dc7dd75..860994129ae 100644
--- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
@@ -22,6 +22,14 @@
bootph-all;
};
+&mu {
+ status = "disabled";
+};
+
+&wdog3 {
+ status = "disabled";
+};
+
&per_bridge4 {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/imx8ulp-evk.dts b/arch/arm/dts/imx8ulp-evk.dts
deleted file mode 100644
index 7aec1706382..00000000000
--- a/arch/arm/dts/imx8ulp-evk.dts
+++ /dev/null
@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2021 NXP
- */
-
-/dts-v1/;
-
-#include "imx8ulp.dtsi"
-
-/ {
- model = "NXP i.MX8ULP EVK";
- compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
-
- chosen {
- stdout-path = &lpuart5;
- };
-
- memory at 80000000 {
- device_type = "memory";
- reg = <0x0 0x80000000 0 0x80000000>;
- };
-
- clock_ext_rmii: clock-ext-rmii {
- compatible = "fixed-clock";
- clock-frequency = <50000000>;
- clock-output-names = "ext_rmii_clk";
- #clock-cells = <0>;
- };
-
- clock_ext_ts: clock-ext-ts {
- compatible = "fixed-clock";
- /* External ts clock is 50MHZ from PHY on EVK board. */
- clock-frequency = <50000000>;
- clock-output-names = "ext_ts_clk";
- #clock-cells = <0>;
- };
-};
-
-&lpuart5 {
- /* console */
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pinctrl_lpuart5>;
- pinctrl-1 = <&pinctrl_lpuart5>;
- status = "okay";
-};
-
-&usdhc0 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pinctrl_usdhc0>;
- pinctrl-1 = <&pinctrl_usdhc0>;
- non-removable;
- bus-width = <8>;
- status = "okay";
-};
-
-&fec {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pinctrl_enet>;
- pinctrl-1 = <&pinctrl_enet>;
- clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
- <&pcc4 IMX8ULP_CLK_ENET>,
- <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
- <&clock_ext_rmii>;
- clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
- assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
- assigned-clock-parents = <&clock_ext_ts>;
- phy-mode = "rmii";
- phy-handle = <ðphy>;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy: ethernet-phy at 1 {
- reg = <1>;
- micrel,led-mode = <1>;
- };
- };
-};
-
-&iomuxc1 {
- pinctrl_enet: enetgrp {
- fsl,pins = <
- MX8ULP_PAD_PTE15__ENET0_MDC 0x43
- MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
- MX8ULP_PAD_PTE17__ENET0_RXER 0x43
- MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
- MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
- MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
- MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
- MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
- MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
- MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43
- MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
- >;
- };
-
- pinctrl_lpuart5: lpuart5grp {
- fsl,pins = <
- MX8ULP_PAD_PTF14__LPUART5_TX 0x3
- MX8ULP_PAD_PTF15__LPUART5_RX 0x3
- >;
- };
-
- pinctrl_usdhc0: usdhc0grp {
- fsl,pins = <
- MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
- MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
- MX8ULP_PAD_PTD10__SDHC0_D0 0x43
- MX8ULP_PAD_PTD9__SDHC0_D1 0x43
- MX8ULP_PAD_PTD8__SDHC0_D2 0x43
- MX8ULP_PAD_PTD7__SDHC0_D3 0x43
- MX8ULP_PAD_PTD6__SDHC0_D4 0x43
- MX8ULP_PAD_PTD5__SDHC0_D5 0x43
- MX8ULP_PAD_PTD4__SDHC0_D6 0x43
- MX8ULP_PAD_PTD3__SDHC0_D7 0x43
- MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
- >;
- };
-};
-
-&wdog3 {
- status = "disabled";
-};
diff --git a/arch/arm/dts/imx8ulp.dtsi b/arch/arm/dts/imx8ulp.dtsi
deleted file mode 100644
index 06ce5f19aa8..00000000000
--- a/arch/arm/dts/imx8ulp.dtsi
+++ /dev/null
@@ -1,476 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2021 NXP
- */
-
-#include <dt-bindings/clock/imx8ulp-clock.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/power/imx8ulp-power.h>
-
-#include "imx8ulp-pinfunc.h"
-
-/ {
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- ethernet0 = &fec;
- gpio0 = &gpiod;
- gpio1 = &gpioe;
- gpio2 = &gpiof;
- mmc0 = &usdhc0;
- mmc1 = &usdhc1;
- mmc2 = &usdhc2;
- serial0 = &lpuart4;
- serial1 = &lpuart5;
- serial2 = &lpuart6;
- serial3 = &lpuart7;
- };
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- A35_0: cpu at 0 {
- device_type = "cpu";
- compatible = "arm,cortex-a35";
- reg = <0x0 0x0>;
- enable-method = "psci";
- next-level-cache = <&A35_L2>;
- };
-
- A35_1: cpu at 1 {
- device_type = "cpu";
- compatible = "arm,cortex-a35";
- reg = <0x0 0x1>;
- enable-method = "psci";
- next-level-cache = <&A35_L2>;
- };
-
- A35_L2: l2-cache0 {
- compatible = "cache";
- };
- };
-
- gic: interrupt-controller at 2d400000 {
- compatible = "arm,gic-v3";
- reg = <0x0 0x2d400000 0 0x10000>, /* GIC Dist */
- <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
- #interrupt-cells = <3>;
- interrupt-controller;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- pmu {
- compatible = "arm,cortex-a35-pmu";
- interrupt-parent = <&gic>;
- interrupts = <GIC_PPI 7
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
- interrupt-affinity = <&A35_0>, <&A35_1>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
- };
-
- frosc: clock-frosc {
- compatible = "fixed-clock";
- clock-frequency = <192000000>;
- clock-output-names = "frosc";
- #clock-cells = <0>;
- };
-
- lposc: clock-lposc {
- compatible = "fixed-clock";
- clock-frequency = <1000000>;
- clock-output-names = "lposc";
- #clock-cells = <0>;
- };
-
- rosc: clock-rosc {
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "rosc";
- #clock-cells = <0>;
- };
-
- sosc: clock-sosc {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "sosc";
- #clock-cells = <0>;
- };
-
- sram at 2201f000 {
- compatible = "mmio-sram";
- reg = <0x0 0x2201f000 0x0 0x1000>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x0 0x2201f000 0x1000>;
-
- scmi_buf: scmi-sram-section at 0 {
- compatible = "arm,scmi-shmem";
- reg = <0x0 0x400>;
- };
- };
-
- firmware {
- scmi {
- compatible = "arm,scmi-smc";
- arm,smc-id = <0xc20000fe>;
- #address-cells = <1>;
- #size-cells = <0>;
- shmem = <&scmi_buf>;
-
- scmi_devpd: protocol at 11 {
- reg = <0x11>;
- #power-domain-cells = <1>;
- };
-
- scmi_sensor: protocol at 15 {
- reg = <0x15>;
- #thermal-sensor-cells = <1>;
- };
- };
- };
-
- soc: soc at 0 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x0 0x40000000>;
-
- s4muap: mailbox at 27020000 {
- compatible = "fsl,imx8ulp-mu-s4";
- reg = <0x27020000 0x10000>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <2>;
- };
-
- per_bridge3: bus at 29000000 {
- compatible = "simple-bus";
- reg = <0x29000000 0x800000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- mu: mailbox at 29220000 {
- compatible = "fsl,imx8ulp-mu";
- reg = <0x29220000 0x10000>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <2>;
- status = "disabled";
- };
-
- mu3: mailbox at 29230000 {
- compatible = "fsl,imx8ulp-mu";
- reg = <0x29230000 0x10000>;
- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc3 IMX8ULP_CLK_MU3_A>;
- #mbox-cells = <2>;
- status = "disabled";
- };
-
- wdog3: watchdog at 292a0000 {
- compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
- reg = <0x292a0000 0x10000>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
- assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
- assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
- timeout-sec = <40>;
- };
-
- cgc1: clock-controller at 292c0000 {
- compatible = "fsl,imx8ulp-cgc1";
- reg = <0x292c0000 0x10000>;
- #clock-cells = <1>;
- };
-
- pcc3: clock-controller at 292d0000 {
- compatible = "fsl,imx8ulp-pcc3";
- reg = <0x292d0000 0x10000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- tpm5: tpm at 29340000 {
- compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
- reg = <0x29340000 0x1000>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
- <&pcc3 IMX8ULP_CLK_TPM5>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- lpi2c4: i2c at 29370000 {
- compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x29370000 0x10000>;
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
- <&pcc3 IMX8ULP_CLK_LPI2C4>;
- clock-names = "per", "ipg";
- assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
- assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
- assigned-clock-rates = <48000000>;
- status = "disabled";
- };
-
- lpi2c5: i2c at 29380000 {
- compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x29380000 0x10000>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
- <&pcc3 IMX8ULP_CLK_LPI2C5>;
- clock-names = "per", "ipg";
- assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
- assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
- assigned-clock-rates = <48000000>;
- status = "disabled";
- };
-
- lpuart4: serial at 29390000 {
- compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x29390000 0x1000>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
- clock-names = "ipg";
- status = "disabled";
- };
-
- lpuart5: serial at 293a0000 {
- compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x293a0000 0x1000>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
- clock-names = "ipg";
- status = "disabled";
- };
-
- lpspi4: spi at 293b0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
- reg = <0x293b0000 0x10000>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
- <&pcc3 IMX8ULP_CLK_LPSPI4>;
- clock-names = "per", "ipg";
- assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
- assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
- assigned-clock-rates = <48000000>;
- status = "disabled";
- };
-
- lpspi5: spi at 293c0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
- reg = <0x293c0000 0x10000>;
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
- <&pcc3 IMX8ULP_CLK_LPSPI5>;
- clock-names = "per", "ipg";
- assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
- assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
- assigned-clock-rates = <48000000>;
- status = "disabled";
- };
- };
-
- per_bridge4: bus at 29800000 {
- compatible = "simple-bus";
- reg = <0x29800000 0x800000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- pcc4: clock-controller at 29800000 {
- compatible = "fsl,imx8ulp-pcc4";
- reg = <0x29800000 0x10000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- lpi2c6: i2c at 29840000 {
- compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x29840000 0x10000>;
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
- <&pcc4 IMX8ULP_CLK_LPI2C6>;
- clock-names = "per", "ipg";
- assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
- assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
- assigned-clock-rates = <48000000>;
- status = "disabled";
- };
-
- lpi2c7: i2c at 29850000 {
- compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
- reg = <0x29850000 0x10000>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
- <&pcc4 IMX8ULP_CLK_LPI2C7>;
- clock-names = "per", "ipg";
- assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
- assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
- assigned-clock-rates = <48000000>;
- status = "disabled";
- };
-
- lpuart6: serial at 29860000 {
- compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x29860000 0x1000>;
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
- clock-names = "ipg";
- status = "disabled";
- };
-
- lpuart7: serial at 29870000 {
- compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
- reg = <0x29870000 0x1000>;
- interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
- clock-names = "ipg";
- status = "disabled";
- };
-
- iomuxc1: pinctrl at 298c0000 {
- compatible = "fsl,imx8ulp-iomuxc1";
- reg = <0x298c0000 0x10000>;
- };
-
- usdhc0: mmc at 298d0000 {
- compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
- reg = <0x298d0000 0x10000>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
- <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
- <&pcc4 IMX8ULP_CLK_USDHC0>;
- clock-names = "ipg", "ahb", "per";
- power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step = <2>;
- bus-width = <4>;
- status = "disabled";
- };
-
- usdhc1: mmc at 298e0000 {
- compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
- reg = <0x298e0000 0x10000>;
- interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
- <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
- <&pcc4 IMX8ULP_CLK_USDHC1>;
- clock-names = "ipg", "ahb", "per";
- power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step = <2>;
- bus-width = <4>;
- status = "disabled";
- };
-
- usdhc2: mmc at 298f0000 {
- compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
- reg = <0x298f0000 0x10000>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
- <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
- <&pcc4 IMX8ULP_CLK_USDHC2>;
- clock-names = "ipg", "ahb", "per";
- power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step = <2>;
- bus-width = <4>;
- status = "disabled";
- };
-
- fec: ethernet at 29950000 {
- compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
- reg = <0x29950000 0x10000>;
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "int0";
- fsl,num-tx-queues = <1>;
- fsl,num-rx-queues = <1>;
- status = "disabled";
- };
- };
-
- gpioe: gpio at 2d000080 {
- compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
- reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
- <&pcc4 IMX8ULP_CLK_PCTLE>;
- clock-names = "gpio", "port";
- gpio-ranges = <&iomuxc1 0 32 24>;
- };
-
- gpiof: gpio at 2d010080 {
- compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
- reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
- <&pcc4 IMX8ULP_CLK_PCTLF>;
- clock-names = "gpio", "port";
- gpio-ranges = <&iomuxc1 0 64 32>;
- };
-
- per_bridge5: bus at 2d800000 {
- compatible = "simple-bus";
- reg = <0x2d800000 0x800000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- cgc2: clock-controller at 2da60000 {
- compatible = "fsl,imx8ulp-cgc2";
- reg = <0x2da60000 0x10000>;
- #clock-cells = <1>;
- };
-
- pcc5: clock-controller at 2da70000 {
- compatible = "fsl,imx8ulp-pcc5";
- reg = <0x2da70000 0x10000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
- };
-
- gpiod: gpio at 2e200080 {
- compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
- reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <2>;
- clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,
- <&pcc5 IMX8ULP_CLK_RGPIOD>;
- clock-names = "gpio", "port";
- gpio-ranges = <&iomuxc1 0 0 24>;
- };
- };
-};
diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig
index e96e34651ce..d64cfca0408 100644
--- a/arch/arm/mach-imx/imx8ulp/Kconfig
+++ b/arch/arm/mach-imx/imx8ulp/Kconfig
@@ -28,6 +28,7 @@ config TARGET_IMX8ULP_EVK
select SUPPORT_SPL
select IMX8ULP_DRAM
imply BOOTSTD_FULL
+ imply OF_UPSTREAM
endchoice
diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig
index f8a87dde5cf..469ee928129 100644
--- a/configs/imx8ulp_evk_defconfig
+++ b/configs/imx8ulp_evk_defconfig
@@ -10,7 +10,7 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x400000
CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx8ulp/imximage.cfg"
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8ulp-evk"
CONFIG_TARGET_IMX8ULP_EVK=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_SERIAL=y
--
2.43.0
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