[PATCH v2 0/9] mmc: sdhci-cadence: Improvements and fixes for Cadence SDHCI driver

[Tanmay Kathpalia]

This v2 series updates the Cadence SDHCI driver and related MMC code to
improve timing mode handling, device tree integration, SD/eMMC tuning,
and alignment with newer SDHCI specification versions.

Changes in v2:

- Updated patch 1 (reset control support): avoid calling
  reset_deassert_bulk() when reset_get_bulk() failed — only deassert
  resets on successful reset_get_bulk().

- Added a new patch in mmc-uclass to explicitly default cfg->f_max to 0
  when the "max-frequency" property is not present. This ensures that
  sdhci_setup_cfg() correctly falls back to the controller’s capability
  registers for the maximum clock rate.

- Adjusted patch ordering so the mmc-uclass behavior is defined before
  the Cadence driver uses it.

- All other patches are carried forward unchanged from v1.

Thanks to Peng Fan for the review and suggestions.

Link to v1:
https://lore.kernel.org/u-boot/20251110173737.24545-1-tanmay.kathpalia@altera.com/

Summary of changes:

- Add reset control support
  Ensures proper controller reset during probe for reliable initialization.

- Add max-frequency handling in mmc-uclass
  Defaults cfg->f_max to 0 when the property is absent so host drivers
  correctly fall back to controller capabilities.

- Respect max-frequency from device tree in Cadence SDHCI
  Uses the max-frequency property when present, and falls back to the
  controller's maximum base clock from the capabilities register when not.

- Correct timing mode and PHY/control configuration
  Refactors timing mode selection for SD and eMMC cards, implements new
  mode mapping, and updates PHY/control settings for UHS and legacy modes.

- Add SDHCI_SPEC_400, _410, and _420 defines
  Introduces new specification macros for SDHCI v4.0+ compatibility.

- Use hardware version field for controller detection
  Switches from compatible string checks to hardware version detection for
  controller capabilities.

- Enable software tuning for SD and eMMC
  Extends tuning logic to support both SD and eMMC devices, improving
  reliability.

- Fix device tree property naming conventions
  Updates DT property names for compliance and corrects minor typos.

- Add DLL master control and improve tuning reliability
  Adds support for PHY DLL master control and enhances tuning robustness.

Regards,
Tanmay Kathpalia
tanmay.kathpalia at altera.com

Tanmay Kathpalia (9):
  mmc: sdhci-cadence: Add reset control support
  mmc: mmc-uclass: Use max-frequency from device tree with default
    handling
  mmc: sdhci-cadence: Use max-frequency property from device tree
  mmc: sdhci-cadence: Set controller and PHY speed modes for SD and eMMC
    cards
  mmc: sdhci: Add SDHCI_SPEC_400, _410, and _420 version defines
  mmc: sdhci-cadence: Use hardware version field for Cadence SDHCI
    controller
  mmc: sdhci-cadence: Enable software tuning for both SD and eMMC
    interfaces
  mmc: sdhci-cadence6: socfpga: Fix DT property naming convention
  mmc: sdhci-cadence6: Add DLL master control and improve tuning
    reliability

 drivers/mmc/mmc-uclass.c     |  9 +++-
 drivers/mmc/sdhci-cadence.c  | 98 +++++++++++++++++++++++++-----------
 drivers/mmc/sdhci-cadence6.c | 82 +++++++++++++++++++++++-------
 include/sdhci.h              |  3 ++
 4 files changed, 142 insertions(+), 50 deletions(-)

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2.43.7