[PATCH 1/2] riscv: create a custom CPU implementation for PolarFire SoC

[Leo Liang]

Hi Jamie,

On Wed, Nov 19, 2025 at 12:38:42PM +0000, Jamie Gibbons wrote:
> [EXTERNAL MAIL]
> 
> From: Conor Dooley <conor.dooley at microchip.com>
> 
> PolarFire SoC needs a custom implementation of top_of_ram(), so stop
> using the generic CPU & create a custom CPU instead.
> 
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
>  arch/riscv/Kconfig                     |  1 +
>  arch/riscv/cpu/mpfs/Kconfig            | 16 +++++++++++
>  arch/riscv/cpu/mpfs/Makefile           |  6 ++++
>  arch/riscv/cpu/mpfs/cpu.c              | 22 +++++++++++++++
>  arch/riscv/cpu/mpfs/dram.c             | 38 ++++++++++++++++++++++++++
>  arch/riscv/include/asm/arch-mpfs/clk.h |  8 ++++++
>  board/microchip/mpfs_generic/Kconfig   |  4 +--
>  7 files changed, 93 insertions(+), 2 deletions(-)
>  create mode 100644 arch/riscv/cpu/mpfs/Kconfig
>  create mode 100644 arch/riscv/cpu/mpfs/Makefile
>  create mode 100644 arch/riscv/cpu/mpfs/cpu.c

The cpu.c file only contains "cleanup_before_linux" and seems identical
with the one provided in arch/riscv/cpu/generic/cpu.c.

Other than that, LGTM.

If you don't mind, I could fix this on my side that you don't need to
resend the patchset again.

Reviewed-by: Leo Yu-Chi Liang <ycliang at andestech.com>