[PATCH v2 9/9] mmc: sdhci-cadence6: Add DLL master control and improve tuning reliability

[Peng Fan]

On Wed, Dec 03, 2025 at 04:21:39AM -0800, Tanmay Kathpalia wrote:
>- Add support for configuring the PHY DLL master control register for all
>  SD/eMMC timing modes (DS, HS, SDR, DDR, HS200, HS400) by extending the
>  PHY configuration arrays and writing the value during PHY adjustment.
>- Fix tuning reliability by toggling the DLL reset before and after
>  updating the PHY_DLL_SLAVE_CTRL_REG_ADDR register.
>
>Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia at altera.com>
>Reviewed-by: Balsundar Ponnusamy <balsundar.ponnusamy at altera.com>

Acked-by: Peng Fan <peng.fan at nxp.com>