[PATCH] xilinx: mbv: Update defconfigs as per memory map

[Michal Simek]

On 12/8/25 16:03, Michal Simek wrote:
> From: Padmarao Begari <padmarao.begari at amd.com>
> 
> U-Boot SPL should be executed from LMB BRAM, where its text
> and data sections are located, while the heap and stack are
> allocated in DDR memory.
> 
> Because on the MB-V platform, after power-up, reset, or FPGA
> load, execution begins from LMB BRAM at address 0x0. Therefore,
> the SPL binary must be placed in BRAM to support this boot flow.
> Without it, the system can only be booted via JTAG.
> 
> A 64KB LMB BRAM region is allocated for U-Boot SPL, starting at
> address 0x0. This region contains the SPL's text, data, and device
> tree blob (DTB) sections. The .bss section is placed separately at
> address 0xF000.
> 
> 	_________________0xFFFF
> 	|BSS            |
> 	|_______________|0xF000
> 	|DTB            |
> 	|_______________|
> 	|Data           |
> 	|_______________|
> 	|Text           |
> 	|_______________|0x0000
> 
> A 2MB region of DDR memory is allocated for U-Boot SPL, with the
> heap starting at address 0x80000000 and the stack at 0x80200000.
> 
> 	_________________0xBFFFFFFF
> 	|Full U-Boot    |
> 	|_______________|0x80400000
> 	|Load FIT Image |
> 	|_______________|0x80200000
> 	|Stack          |
> 	|_______________|
> 	|Heap           |
> 	|_______________|0x80000000
> 
> Since LMB BRAM is a limited resource with a practical size
> constraint of 64KB - it cannot accommodate all runtime data.
> Therefore, the heap and stack are placed at the beginning of
> DDR memory to ensure sufficient space for SPL execution.
> 
> Signed-off-by: Padmarao Begari <padmarao.begari at amd.com>
> Signed-off-by: Michal Simek <michal.simek at amd.com>
> ---
> 
>   configs/xilinx_mbv32_defconfig | 12 ++++++++----
>   1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig
> index 9e3c44352a15..42dc5fb282ad 100644
> --- a/configs/xilinx_mbv32_defconfig
> +++ b/configs/xilinx_mbv32_defconfig
> @@ -6,11 +6,12 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
>   CONFIG_ENV_SIZE=0x20000
>   CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
>   CONFIG_SPL_STACK=0x80200000
> -CONFIG_SPL_BSS_START_ADDR=0x84000000
> -CONFIG_SPL_BSS_MAX_SIZE=0x80000
> +CONFIG_SPL_TEXT_BASE=0x0
> +CONFIG_SPL_BSS_START_ADDR=0xf000
> +CONFIG_SPL_BSS_MAX_SIZE=0x1000
>   CONFIG_SYS_BOOTM_LEN=0x800000
>   CONFIG_SYS_LOAD_ADDR=0x80200000
> -CONFIG_SPL_SIZE_LIMIT=0x40000
> +CONFIG_SPL_SIZE_LIMIT=0x10000
>   CONFIG_SPL=y
>   CONFIG_SYS_CLK_FREQ=100000000
>   CONFIG_BOOT_SCRIPT_OFFSET=0x0
> @@ -25,10 +26,13 @@ CONFIG_DISPLAY_CPUINFO=y
>   CONFIG_DISPLAY_BOARDINFO=y
>   # CONFIG_BOARD_INIT is not set
>   # CONFIG_BOARD_LATE_INIT is not set
> -CONFIG_SPL_MAX_SIZE=0x40000
> +CONFIG_SPL_MAX_SIZE=0xf000
>   # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
>   CONFIG_SPL_HAVE_INIT_STACK=y
>   CONFIG_SPL_SYS_MALLOC=y
> +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
> +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
> +CONFIG_SPL_SYS_MALLOC_SIZE=0x200000
>   # CONFIG_CMD_MII is not set
>   CONFIG_CMD_SNTP=y
>   CONFIG_CMD_TIMER=y

Applied.
M