[RESEND v2 1/6] clk/qcom: Add USB related clocks for IPQ9574

[Sumit Garg]

On Thu, Dec 18, 2025 at 11:45:52AM +0530, Varadarajan Narayanan wrote:
> Add the USB controller and phy related clocks.
> 
> Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan at oss.qualcomm.com>
> ---
>  drivers/clk/qcom/clock-ipq9574.c | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
>

Acked-by: Sumit Garg <sumit.garg at oss.qualcomm.com>

-Sumit

> diff --git a/drivers/clk/qcom/clock-ipq9574.c b/drivers/clk/qcom/clock-ipq9574.c
> index b0af4036059..1f5146b29a1 100644
> --- a/drivers/clk/qcom/clock-ipq9574.c
> +++ b/drivers/clk/qcom/clock-ipq9574.c
> @@ -25,6 +25,9 @@
>  #define GCC_SDCC1_AHB_CBCR			0x33034
>  #define GCC_SDCC1_APPS_CMD_RCGR			0x33004
>  #define GCC_SDCC1_ICE_CORE_CBCR			0x33030
> +#define GCC_USB0_MASTER_CMD_RCGR		0x2c004
> +#define GCC_USB0_MOCK_UTMI_CMD_RCGR		0x2c02c
> +#define GCC_USB0_AUX_CMD_RCGR			0x2C018
>  
>  static ulong ipq9574_set_rate(struct clk *clk, ulong rate)
>  {
> @@ -39,6 +42,17 @@ static ulong ipq9574_set_rate(struct clk *clk, ulong rate)
>  		clk_rcg_set_rate_mnd(priv->base, GCC_SDCC1_APPS_CMD_RCGR,
>  				     11, 0, 0, CFG_CLK_SRC_GPLL2, 16);
>  		return rate;
> +	case GCC_USB0_MASTER_CLK:
> +		clk_rcg_set_rate(priv->base, GCC_USB0_MASTER_CMD_RCGR,
> +				 4, CFG_CLK_SRC_GPLL0);
> +		return rate;
> +	case GCC_USB0_MOCK_UTMI_CLK:
> +		clk_rcg_set_rate_mnd(priv->base, GCC_USB0_MOCK_UTMI_CMD_RCGR,
> +				     0, 0, 0, CFG_CLK_SRC_CXO, 8);
> +		return rate;
> +	case GCC_USB0_AUX_CLK:
> +		clk_rcg_set_rate_mnd(priv->base, GCC_USB0_AUX_CMD_RCGR, 0, 0, 0,
> +				     CFG_CLK_SRC_CXO, 8);
>  	default:
>  		return -EINVAL;
>  	}
> @@ -50,6 +64,14 @@ static const struct gate_clk ipq9574_clks[] = {
>  	GATE_CLK(GCC_SDCC1_AHB_CLK,		0x33034, 0x00000001),
>  	GATE_CLK(GCC_SDCC1_APPS_CLK,		0x3302C, 0x00000001),
>  	GATE_CLK(GCC_SDCC1_ICE_CORE_CLK,	0x33030, 0x00000001),
> +	GATE_CLK(GCC_SNOC_USB_CLK,		0x2e058, 0x00000001),
> +	GATE_CLK(GCC_USB0_MASTER_CLK,		0x2c044, 0x00000001),
> +	GATE_CLK(GCC_ANOC_USB_AXI_CLK,		0x2e084, 0x00000001),
> +	GATE_CLK(GCC_USB0_SLEEP_CLK,		0x2c058, 0x00000001),
> +	GATE_CLK(GCC_USB0_MOCK_UTMI_CLK,	0x2c04c, 0x00000001),
> +	GATE_CLK(GCC_USB0_PHY_CFG_AHB_CLK,	0x2c05c, 0x00000001),
> +	GATE_CLK(GCC_USB0_AUX_CLK,		0x2c048, 0x00000001),
> +	GATE_CLK(GCC_USB0_PIPE_CLK,		0x2c054, 0x00000001),
>  };
>  
>  static int ipq9574_enable(struct clk *clk)
> @@ -67,6 +89,10 @@ static int ipq9574_enable(struct clk *clk)
>  }
>  
>  static const struct qcom_reset_map ipq9574_gcc_resets[] = {
> +	[GCC_USB_BCR] = { 0x2c000 },
> +	[GCC_QUSB2_0_PHY_BCR] = { 0x2c068 },
> +	[GCC_USB0_PHY_BCR] = {0x2c06c, 0},
> +	[GCC_USB3PHY_0_PHY_BCR] = {0x2c070, 0},
>  	[GCC_SDCC_BCR] = { 0x33000 },
>  };
>  
> @@ -75,6 +101,8 @@ static struct msm_clk_data ipq9574_gcc_data = {
>  	.num_resets = ARRAY_SIZE(ipq9574_gcc_resets),
>  	.enable = ipq9574_enable,
>  	.set_rate = ipq9574_set_rate,
> +	.clks = ipq9574_clks,
> +	.num_clks = ARRAY_SIZE(ipq9574_clks),
>  };
>  
>  static const struct udevice_id gcc_ipq9574_of_match[] = {
> -- 
> 2.34.1
>