[PATCH 1/5] rockchip: sdram: add option to read bank information from TPL

Aaron Griffith aargri at gmail.com
Mon Dec 29 01:05:23 CET 2025


Existing code to read DDR_MEM tags from the Rockchip external TPL is
gated behind CONFIG_ARM64. These changes instead place it behind a new
config, ROCKCHIP_EXTERNAL_TPL_DDR_MEM. This option is implied by the
four SoCs that currently use this feature (RK3528, RK3568, RK3576, and
RK3588).

Signed-off-by: Aaron Griffith <aargri at gmail.com>
---
 arch/arm/mach-rockchip/Kconfig | 11 +++++++++++
 arch/arm/mach-rockchip/sdram.c | 12 +++++++-----
 2 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index e32e49ff59acc633feba96f8870754b60fc366c6..1f80ff3136e2bb565a2f4be59d9b025dd0d70d95 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -348,6 +348,7 @@ config ROCKCHIP_RK3528
 	imply ROCKCHIP_COMMON_BOARD
 	imply ROCKCHIP_COMMON_STACK_ADDR
 	imply ROCKCHIP_EXTERNAL_TPL
+	imply ROCKCHIP_EXTERNAL_TPL_DDR_MEM
 	imply ROCKCHIP_OTP
 	imply SPL_ATF
 	imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
@@ -392,6 +393,7 @@ config ROCKCHIP_RK3568
 	imply ROCKCHIP_COMMON_BOARD
 	imply ROCKCHIP_COMMON_STACK_ADDR
 	imply ROCKCHIP_EXTERNAL_TPL
+	imply ROCKCHIP_EXTERNAL_TPL_DDR_MEM
 	imply ROCKCHIP_OTP
 	imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
 	imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
@@ -432,6 +434,7 @@ config ROCKCHIP_RK3576
 	imply ROCKCHIP_COMMON_BOARD
 	imply ROCKCHIP_COMMON_STACK_ADDR
 	imply ROCKCHIP_EXTERNAL_TPL
+	imply ROCKCHIP_EXTERNAL_TPL_DDR_MEM
 	imply ROCKCHIP_OTP
 	imply SPL_ATF
 	imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
@@ -477,6 +480,7 @@ config ROCKCHIP_RK3588
 	imply ROCKCHIP_COMMON_BOARD
 	imply ROCKCHIP_COMMON_STACK_ADDR
 	imply ROCKCHIP_EXTERNAL_TPL
+	imply ROCKCHIP_EXTERNAL_TPL_DDR_MEM
 	imply ROCKCHIP_OTP
 	imply SCMI_FIRMWARE
 	imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
@@ -608,6 +612,13 @@ config ROCKCHIP_EXTERNAL_TPL
 	  Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
 	  include the external TPL in the image built by binman.
 
+config ROCKCHIP_EXTERNAL_TPL_DDR_MEM
+	bool "Use DDR_MEM information from external TPL"
+	depends on ROCKCHIP_EXTERNAL_TPL
+	help
+	  Some Rockchip external TPLs provide information about DDR memory.
+	  Enable this option to parse and use this information.
+
 config ROCKCHIP_BOOT_MODE_REG
 	hex "Rockchip boot mode flag register address"
 	help
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index d560f90e873d02e1a799ab0d7c1e085df0c1c54a..f549baaa8e7e0664029f37de012dd22dfe92b07f 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -36,7 +36,7 @@ struct tos_parameter_t {
 	s64 reserve[8];
 };
 
-#ifdef CONFIG_ARM64
+#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL_DDR_MEM
 /* Tag size and offset */
 #define ATAGS_SIZE		SZ_8K
 #define ATAGS_OFFSET		(SZ_2M - ATAGS_SIZE)
@@ -287,14 +287,14 @@ static int rockchip_dram_init_banksize(void)
 
 	return 0;
 }
-#endif
+#endif /* CONFIG_ROCKCHIP_EXTERNAL_TPL_DDR_MEM */
 
 int dram_init_banksize(void)
 {
 	size_t ram_top = (unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE);
 	size_t top = min((unsigned long)ram_top, (unsigned long)(gd->ram_top));
 
-#ifdef CONFIG_ARM64
+#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL_DDR_MEM
 	int ret = rockchip_dram_init_banksize();
 
 	if (!ret)
@@ -302,7 +302,9 @@ int dram_init_banksize(void)
 
 	debug("Couldn't use ATAG (%d) to detect DDR layout, falling back...\n",
 	      ret);
+#endif
 
+#ifdef CONFIG_ARM64
 	/* Reserve 2M for ATF bl31 */
 	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + SZ_2M;
 	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
@@ -314,7 +316,7 @@ int dram_init_banksize(void)
 	} else if (ram_top > SZ_4G && top == SZ_4G) {
 		gd->bd->bi_dram[0].size = ram_top - gd->bd->bi_dram[0].start;
 	}
-#else
+#else /* !CONFIG_ARM64 */
 #ifdef CONFIG_SPL_OPTEE_IMAGE
 	struct tos_parameter_t *tos_parameter;
 
@@ -340,7 +342,7 @@ int dram_init_banksize(void)
 	gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
 	gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
 #endif
-#endif
+#endif /* CONFIG_ARM64 */
 
 	return 0;
 }

-- 
2.47.3



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