[PATCH 4/9] clk: mediatek: fix fixed clock parents

[Julien Stephan]

Le ven. 19 déc. 2025 à 00:24, David Lechner <dlechner at baylibre.com> a écrit :
>
> Add a flags field to struct mtk_fixed_clk to allow properly resolving
> the parent clock. All chip-specific clocks are updated to populate this
> field correctly.
>
> The parent is currently only used for printing debug information, so
> there are no functional bugs being fixed.
>
> Signed-off-by: David Lechner <dlechner at baylibre.com>
> ---
>  drivers/clk/mediatek/clk-mt7622.c | 23 +++++++++++++----------
>  drivers/clk/mediatek/clk-mt7623.c | 33 ++++++++++++++++++---------------
>  drivers/clk/mediatek/clk-mt7629.c | 23 +++++++++++++----------
>  drivers/clk/mediatek/clk-mt7981.c | 21 ++++++++++++---------
>  drivers/clk/mediatek/clk-mt7986.c | 21 ++++++++++++---------
>  drivers/clk/mediatek/clk-mt7987.c | 19 +++++++++++--------
>  drivers/clk/mediatek/clk-mt7988.c | 29 ++++++++++++++++-------------
>  drivers/clk/mediatek/clk-mt8183.c | 12 +++++++++---
>  drivers/clk/mediatek/clk-mt8365.c | 16 +++++++++++-----
>  drivers/clk/mediatek/clk-mt8512.c |  7 +++++--
>  drivers/clk/mediatek/clk-mt8516.c | 12 +++++++++---
>  drivers/clk/mediatek/clk-mt8518.c | 14 ++++++++++----
>  drivers/clk/mediatek/clk-mtk.c    |  3 +--
>  drivers/clk/mediatek/clk-mtk.h    |  4 +++-
>  14 files changed, 143 insertions(+), 94 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
> index 9621d5efe11..93e87ee399d 100644
> --- a/drivers/clk/mediatek/clk-mt7622.c
> +++ b/drivers/clk/mediatek/clk-mt7622.c
> @@ -85,6 +85,9 @@ static const struct mtk_gate apmixed_cgs[] = {
>  };
>
>  /* topckgen */
> +#define FIXED_CLK0(_id, _rate)                                 \
> +       FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL _rate)
> +

Hi David,

There is a typo here: s/CLK_PARENT_XTAL _rate/CLK_PARENT_XTAL_, rate

>  #define FACTOR0(_id, _parent, _mult, _div)                     \
>         FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
>
> @@ -95,16 +98,16 @@ static const struct mtk_gate apmixed_cgs[] = {
>         FACTOR(_id, _parent, _mult, _div, 0)
>
>  static const struct mtk_fixed_clk top_fixed_clks[] = {
> -       FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000),
> -       FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000),
> -       FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000),
> -       FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000),
> -       FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000),
> -       FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000),
> -       FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333),
> -       FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000),
> -       FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000),
> -       FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000),
> +       FIXED_CLK0(CLK_TOP_TO_U2_PHY, 31250000),
> +       FIXED_CLK0(CLK_TOP_TO_U2_PHY_1P, 31250000),
> +       FIXED_CLK0(CLK_TOP_PCIE0_PIPE_EN, 125000000),
> +       FIXED_CLK0(CLK_TOP_PCIE1_PIPE_EN, 125000000),
> +       FIXED_CLK0(CLK_TOP_SSUSB_TX250M, 250000000),
> +       FIXED_CLK0(CLK_TOP_SSUSB_EQ_RX250M, 250000000),
> +       FIXED_CLK0(CLK_TOP_SSUSB_CDR_REF, 33333333),
> +       FIXED_CLK0(CLK_TOP_SSUSB_CDR_FB, 50000000),
> +       FIXED_CLK0(CLK_TOP_SATA_ASIC, 50000000),
> +       FIXED_CLK0(CLK_TOP_SATA_RBC, 50000000),
>  };
>
>  static const struct mtk_fixed_factor top_fixed_divs[] = {
> diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
> index 3509ea67e7d..093577c4ee4 100644
> --- a/drivers/clk/mediatek/clk-mt7623.c
> +++ b/drivers/clk/mediatek/clk-mt7623.c
> @@ -259,6 +259,9 @@ static const int top_id_offs_map[CLK_TOP_NR + 1] = {
>         [CLK_TOP_AUD_I2S6_MCLK]                 = 158,
>  };
>
> +#define FIXED_CLK0(_id, _rate)                                 \
> +       FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL _rate)
> +

same here.

Cheers
Julien