[PATCH 1/2] mtd: spi: simplify the conditional compilation of quad_enable feature
Shiji Yang
yangshiji66 at outlook.com
Wed Dec 31 13:32:32 CET 2025
Introduce new SNOR_SR1_BIT6_QUAD_ENABLE and SNOR_SR2_BIT1_QUAD_ENABLE
macro definitions to guard the quad_enable codes. This can make the
review easier. It's also a preparation for introducing the new Flash
vendor BoyaMicro.
Signed-off-by: Shiji Yang <yangshiji66 at outlook.com>
---
drivers/mtd/spi/spi-nor-core.c | 28 +++++++++++++++++++---------
drivers/mtd/spi/spi-nor-tiny.c | 27 +++++++++++++++++----------
2 files changed, 36 insertions(+), 19 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 76c33b24368..5fa7ba27ae5 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -188,6 +188,16 @@ struct sfdp_header {
/* Status, Control and Configuration Register Map(SCCR) */
#define SCCR_DWORD22_OCTAL_DTR_EN_VOLATILE BIT(31)
+#if IS_ENABLED(CONFIG_SPI_FLASH_ISSI) || \
+ IS_ENABLED(CONFIG_SPI_FLASH_MACRONIX)
+#define SNOR_SR1_BIT6_QUAD_ENABLE
+#endif
+
+#if IS_ENABLED(CONFIG_SPI_FLASH_SPANSION) || \
+ IS_ENABLED(CONFIG_SPI_FLASH_WINBOND)
+#define SNOR_SR2_BIT1_QUAD_ENABLE
+#endif
+
struct sfdp_bfpt {
u32 dwords[BFPT_DWORD_MAX];
};
@@ -578,7 +588,7 @@ static int read_fsr(struct spi_nor *nor)
* location. Return the configuration register value.
* Returns negative if error occurred.
*/
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+#ifdef SNOR_SR2_BIT1_QUAD_ENABLE
static int read_cr(struct spi_nor *nor)
{
int ret;
@@ -2110,7 +2120,7 @@ write_err:
return ret;
}
-#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
+#ifdef SNOR_SR1_BIT6_QUAD_ENABLE
/**
* macronix_quad_enable() - set QE bit in Status Register.
* @nor: pointer to a 'struct spi_nor'
@@ -2204,7 +2214,7 @@ static int spansion_quad_enable_volatile(struct spi_nor *nor, u32 addr_base,
}
#endif
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+#ifdef SNOR_SR2_BIT1_QUAD_ENABLE
/*
* Write status Register and configuration register with 2 bytes
* The first byte will be written to the status register, while the
@@ -2319,7 +2329,7 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
}
#endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
-#endif /* CONFIG_SPI_FLASH_SPANSION */
+#endif /* SNOR_SR2_BIT1_QUAD_ENABLE */
static void
spi_nor_set_read_settings(struct spi_nor_read_command *read,
@@ -2710,18 +2720,18 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
case BFPT_DWORD15_QER_NONE:
params->quad_enable = NULL;
break;
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+#ifdef SNOR_SR2_BIT1_QUAD_ENABLE
case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
params->quad_enable = spansion_no_read_cr_quad_enable;
break;
#endif
-#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
+#ifdef SNOR_SR1_BIT6_QUAD_ENABLE
case BFPT_DWORD15_QER_SR1_BIT6:
params->quad_enable = macronix_quad_enable;
break;
#endif
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+#ifdef SNOR_SR2_BIT1_QUAD_ENABLE
case BFPT_DWORD15_QER_SR2_BIT1:
params->quad_enable = spansion_read_cr_quad_enable;
break;
@@ -3155,7 +3165,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
SNOR_HWCAPS_PP_QUAD)) {
switch (JEDEC_MFR(info)) {
-#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
+#ifdef SNOR_SR1_BIT6_QUAD_ENABLE
case SNOR_MFR_MACRONIX:
case SNOR_MFR_ISSI:
params->quad_enable = macronix_quad_enable;
@@ -3166,7 +3176,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
break;
default:
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+#ifdef SNOR_SR2_BIT1_QUAD_ENABLE
/* Kept only for backward compatibility purpose. */
params->quad_enable = spansion_read_cr_quad_enable;
#endif
diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c
index 23de64a1520..dde290ca6a4 100644
--- a/drivers/mtd/spi/spi-nor-tiny.c
+++ b/drivers/mtd/spi/spi-nor-tiny.c
@@ -36,6 +36,15 @@
#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
+#if IS_ENABLED(CONFIG_SPI_FLASH_MACRONIX)
+#define SNOR_SR1_BIT6_QUAD_ENABLE
+#endif
+
+#if IS_ENABLED(CONFIG_SPI_FLASH_SPANSION) || \
+ IS_ENABLED(CONFIG_SPI_FLASH_WINBOND)
+#define SNOR_SR2_BIT1_QUAD_ENABLE
+#endif
+
static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
*op, void *buf)
{
@@ -120,7 +129,7 @@ static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
return len;
}
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+#ifdef SNOR_SR2_BIT1_QUAD_ENABLE
/*
* Read configuration register, returning its value in the
* location. Return the configuration register value.
@@ -253,9 +262,7 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
}
}
-#if defined(CONFIG_SPI_FLASH_SPANSION) || \
- defined(CONFIG_SPI_FLASH_WINBOND) || \
- defined(CONFIG_SPI_FLASH_MACRONIX)
+#if defined(SNOR_SR1_BIT6_QUAD_ENABLE) || defined(SNOR_SR2_BIT1_QUAD_ENABLE)
/*
* Read the status register, returning its value in the location
* Return the status register value.
@@ -356,7 +363,7 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor)
return spi_nor_wait_till_ready_with_timeout(nor,
DEFAULT_READY_WAIT_JIFFIES);
}
-#endif /* CONFIG_SPI_FLASH_SPANSION */
+#endif
/*
* Erase an address range on the nor chip. The address range may extend
@@ -433,7 +440,7 @@ static int spi_nor_write_tiny(struct mtd_info *mtd, loff_t to, size_t len,
return -ENOTSUPP;
}
-#ifdef CONFIG_SPI_FLASH_MACRONIX
+#ifdef SNOR_SR1_BIT6_QUAD_ENABLE
/**
* macronix_quad_enable() - set QE bit in Status Register.
* @nor: pointer to a 'struct spi_nor'
@@ -472,7 +479,7 @@ static int macronix_quad_enable(struct spi_nor *nor)
}
#endif
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+#ifdef SNOR_SR2_BIT1_QUAD_ENABLE
/*
* Write status Register and configuration register with 2 bytes
* The first byte will be written to the status register, while the
@@ -554,7 +561,7 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
return 0;
}
-#endif /* CONFIG_SPI_FLASH_SPANSION */
+#endif /* SNOR_SR2_BIT1_QUAD_ENABLE */
static void
spi_nor_set_read_settings(struct spi_nor_read_command *read,
@@ -662,7 +669,7 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
/* Enable Quad I/O if needed. */
if (spi_nor_get_protocol_width(nor->read_proto) == 4) {
switch (JEDEC_MFR(info)) {
-#ifdef CONFIG_SPI_FLASH_MACRONIX
+#ifdef SNOR_SR1_BIT6_QUAD_ENABLE
case SNOR_MFR_MACRONIX:
err = macronix_quad_enable(nor);
break;
@@ -672,7 +679,7 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
break;
default:
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+#ifdef SNOR_SR2_BIT1_QUAD_ENABLE
/* Kept only for backward compatibility purpose. */
err = spansion_read_cr_quad_enable(nor);
#endif
--
2.51.0
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