[PATCH 0/2] sunxi: clk/mmc: Fix T113-s3 MMC performance

[Andre Przywara]

Hi,

as Kuba reported, the MMC performance of the Allwinner T113-s3 chips in
mainline Linux is only half of what's expected. Checking that in U-Boot
revealed that's actually only one fourth there, since on top of the same
bug as in the kernel, we also calculate the base PLL frequency wrongly.

Fix that by halving the frequency as reported by the clock function, and
apply an extra divider of two in the MMC code - to compensate for that
missing hidden divider (which is the same bug as in Linux).
Seeing only one fourth of the base frequency makes the calculated
internal divider go up by the factor of 4, so we get the MMC performance
back its expected levels: from around 5.8 MB/s to ~23 MB/s.

Cheers,
Andre

Andre Przywara (2):
  sunxi: mmc: Fix T113-s3 MMC clock divider
  sunxi: sun50i_h6: clock: fix PLL_PERIPH0 rate calculation

 arch/arm/mach-sunxi/clock_sun50i_h6.c | 15 ++++++++++-----
 drivers/mmc/sunxi_mmc.c               |  7 +++++++
 2 files changed, 17 insertions(+), 5 deletions(-)

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2.25.1