[PATCH 1/2] sunxi: mmc: Fix T113-s3 MMC clock divider

[Jernej Škrabec]

Dne sreda, 26. februar 2025 ob 12:37:11 Srednjeevropski standardni čas je Andre Przywara napisal(a):
> On the Allwinner D1/R528/T113-s3 SoCs the MMC clock source selected by
> mux value 1 is PLL_PERIPH0(1x), not (2x), as in the other SoCs.
> But we have still the hidden divisor of 2 in the MMC mod clock, so
> need to explicitly compensate for that on those SoCs.
> 
> This leads to the actually programmed clock rate to be double compared
> to before, which increases the MMC performance on those SoCs.
> 
> Signed-off-by: Andre Przywara <andre.przywara at arm.com>
> Reported-by: Kuba Szczodrzyński <kuba at szczodrzynski.pl>

Reviewed-by: Jernej Skrabec <jernej.skrabec at gmail.com>

Best regards,
Jernej