[PATCH] pci: dw_common: Set INCREASE_REGION_SIZE flag based on limit address

[Neil Armstrong]

Hi,

On 06/02/2025 09:49, Neil Armstrong wrote:
> Set the INCREASE_REGION_SIZE for the outbound iATU entry if it
> causes the 4GB range overflow in order to activate the extended
> limit address by means of an additional iATU CSR (upper limit
> address register).
> 
> This is required to make PCIe host controller work on Qualcomm SoCs,
> namely the SM8550 and SM8650.
> 
> Based on the Linux commit 777e7c3ab7303 that can be found at [1].
> 
> [1] https://lore.kernel.org/all/20220624143428.8334-5-Sergey.Semin@baikalelectronics.ru/
> 
> Signed-off-by: Neil Armstrong <neil.armstrong at linaro.org>
> ---
>   drivers/pci/pcie_dw_common.c | 8 ++++++--
>   drivers/pci/pcie_dw_common.h | 2 ++
>   2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c
> index 78961271a8eef8e4b6991675ee9de2bb1968b8da..5322f6bdaee450470d7f706bb4b4097a368ec455 100644
> --- a/drivers/pci/pcie_dw_common.c
> +++ b/drivers/pci/pcie_dw_common.c
> @@ -78,8 +78,12 @@ int pcie_dw_prog_outbound_atu_unroll(struct pcie_dw *pci, int index,
>   				 lower_32_bits(pci_addr));
>   	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
>   				 upper_32_bits(pci_addr));
> -	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
> -				 type);
> +	if (upper_32_bits(cpu_addr + size - 1) > upper_32_bits(cpu_addr))
> +		dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
> +					 type | PCIE_ATU_INCREASE_REGION_SIZE);
> +	else
> +		dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
> +					 type);
>   	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
>   				 PCIE_ATU_ENABLE);
>   
> diff --git a/drivers/pci/pcie_dw_common.h b/drivers/pci/pcie_dw_common.h
> index 8cb99a12ea1a5fd3687f980cc1ff99839d06dbc2..748945f95975e8251cdb92a670e8d5bc575d2847 100644
> --- a/drivers/pci/pcie_dw_common.h
> +++ b/drivers/pci/pcie_dw_common.h
> @@ -46,6 +46,8 @@
>   #define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)
>   #define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
>   
> +#define PCIE_ATU_INCREASE_REGION_SIZE    BIT(13)
> +
>   /* Register address builder */
>   #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region)	((region) << 9)
>   
> 
> ---
> base-commit: b3c09eb36529fbb277bec17b35e638f42cb33683
> change-id: 20250206-topic-sm8x50-pcie-dw-atu-increase-region-size-878465356c54
> 
> Best regards,

Gentle ping, this change is required to make PCIe enumerate
on some the Qualcomm SoCs.

Thanks,
Neil