[PATCH] pci: dw_common: Set INCREASE_REGION_SIZE flag based on limit address

[Tom Rini]

On Fri, Feb 28, 2025 at 04:27:06PM +0100, Neil Armstrong wrote:
> Hi,
> 
> On 06/02/2025 09:49, Neil Armstrong wrote:
> > Set the INCREASE_REGION_SIZE for the outbound iATU entry if it
> > causes the 4GB range overflow in order to activate the extended
> > limit address by means of an additional iATU CSR (upper limit
> > address register).
> > 
> > This is required to make PCIe host controller work on Qualcomm SoCs,
> > namely the SM8550 and SM8650.
> > 
> > Based on the Linux commit 777e7c3ab7303 that can be found at [1].
> > 
> > [1] https://lore.kernel.org/all/20220624143428.8334-5-Sergey.Semin@baikalelectronics.ru/
> > 
> > Signed-off-by: Neil Armstrong <neil.armstrong at linaro.org>
> > ---
> >   drivers/pci/pcie_dw_common.c | 8 ++++++--
> >   drivers/pci/pcie_dw_common.h | 2 ++
> >   2 files changed, 8 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c
> > index 78961271a8eef8e4b6991675ee9de2bb1968b8da..5322f6bdaee450470d7f706bb4b4097a368ec455 100644
> > --- a/drivers/pci/pcie_dw_common.c
> > +++ b/drivers/pci/pcie_dw_common.c
> > @@ -78,8 +78,12 @@ int pcie_dw_prog_outbound_atu_unroll(struct pcie_dw *pci, int index,
> >   				 lower_32_bits(pci_addr));
> >   	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
> >   				 upper_32_bits(pci_addr));
> > -	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
> > -				 type);
> > +	if (upper_32_bits(cpu_addr + size - 1) > upper_32_bits(cpu_addr))
> > +		dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
> > +					 type | PCIE_ATU_INCREASE_REGION_SIZE);
> > +	else
> > +		dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
> > +					 type);
> >   	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
> >   				 PCIE_ATU_ENABLE);
> > diff --git a/drivers/pci/pcie_dw_common.h b/drivers/pci/pcie_dw_common.h
> > index 8cb99a12ea1a5fd3687f980cc1ff99839d06dbc2..748945f95975e8251cdb92a670e8d5bc575d2847 100644
> > --- a/drivers/pci/pcie_dw_common.h
> > +++ b/drivers/pci/pcie_dw_common.h
> > @@ -46,6 +46,8 @@
> >   #define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)
> >   #define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
> > +#define PCIE_ATU_INCREASE_REGION_SIZE    BIT(13)
> > +
> >   /* Register address builder */
> >   #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region)	((region) << 9)
> > 
> > ---
> > base-commit: b3c09eb36529fbb277bec17b35e638f42cb33683
> > change-id: 20250206-topic-sm8x50-pcie-dw-atu-increase-region-size-878465356c54
> > 
> > Best regards,
> 
> Gentle ping, this change is required to make PCIe enumerate
> on some the Qualcomm SoCs.

So I see this is config is use on:
am65x_evm_a53 bananapi-cm4-cm4io bananapi-m2s cm3588-nas-rk3588
coolpi-4b-rk3588s coolpi-cm5-evb-rk3588 coolpi-cm5-genbook-rk3588
imx8mm_data_modul_edm_sbc imx8mm_venice imx8mp_beacon imx8mp_dhcom_pdk3
imx8mp_venice iot2050 jaguar-rk3588 khadas-vim3_android_ab
khadas-vim3_android khadas-vim3 khadas-vim3l_android_ab
khadas-vim3l_android khadas-vim3l nanopc-t6-rk3588 nanopi-r3s-rk3566
nanopi-r5c-rk3568 nanopi-r5s-rk3568 nanopi-r6c-rk3588s
nanopi-r6s-rk3588s nova-rk3588s odroid-hc4 odroid-m1-rk3568
odroid-m1s-rk3566 odroid-m2-rk3588s orangepi-3b-rk3566
orangepi-5-plus-rk3588 orangepi-5-rk3588s phycore-imx8mm
qnap-ts433-rk3568 quartz64-a-rk3566 quartz64-b-rk3566 quartzpro64-rk3588
radxa-e25-rk3568 rock-3a-rk3568 rock-3b-rk3568 rock-3c-rk3566
rock-5-itx-rk3588 rock-5c-rk3588s rock5b-rk3588 sifive_unmatched
sige7-rk3588 soquartz-blade-rk3566 soquartz-cm4-rk3566
soquartz-model-a-rk3566 tiger-rk3588 turing-rk1-rk3588 verdin-imx8mp

I see a few of those are also amlogic boards, did you sanity test there?

-- 
Tom
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