[PATCH] arch: arm: mach-k3: j784s4_init: Set CTRL_MMR for AUDIO_REFCLK1 clk_sel
Jayesh Choudhary
j-choudhary at ti.com
Tue Jan 7 11:36:55 CET 2025
Hello Andrew,
On 06/01/25 20:42, Andrew Davis wrote:
> On 1/6/25 4:04 AM, Jayesh Choudhary wrote:
>> The default value for the mux to select the parent clock,
>> AUDIO_REFCLK1_CTRL_CLK_SEL is '11111' (31) but the mux input for 31
>> is marked as 'Reserved' so the ti-sci-clk call for get-parent fails.
>> Mark it to a valid value, '11100' (28) for MAIN_PLL4_HSDIV2_CLKOUT
>> to get rid of the linux failures during boot-time like:
>
> So the default value of the mux isn't known by firmware? Sounds like
> a firmware issue..
>
> No issue with using the bootloader to making the hardware's default state
> more sane. Maybe just add a comment above the writel() line as right now
> this is just writing a magic value to a magic address.
Will add the comments in v2.
Thanks,
Jayesh
>
> Andrew
>
>> "[ 1.573193] ti-sci-clk 44083000.system-controller:clock-controller:
>> get-parent failed for dev=157, clk=34, ret=-19"
>>
>> Signed-off-by: Jayesh Choudhary <j-choudhary at ti.com>
>> ---
>> arch/arm/mach-k3/j784s4/j784s4_init.c | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c
>> b/arch/arm/mach-k3/j784s4/j784s4_init.c
>> index 8a41cd3bb5..787cf6261e 100644
>> --- a/arch/arm/mach-k3/j784s4/j784s4_init.c
>> +++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
>> @@ -23,6 +23,9 @@
>> #define J784S4_MAX_DDR_CONTROLLERS 4
>> +#define CTRL_MMR_CFG0_AUDIO_REFCLK1_CTRL 0x001082e4
>> +#define AUDIO_REFCLK1_DEFAULT 0x1c
>> +
>> /* NAVSS North Bridge (NB) */
>> #define NAVSS0_NBSS_NB0_CFG_MMRS 0x03702000
>> #define NAVSS0_NBSS_NB1_CFG_MMRS 0x03703000
>> @@ -201,6 +204,8 @@ void k3_spl_init(void)
>> remove_fwl_configs(navss_cbass0_fwls,
>> ARRAY_SIZE(navss_cbass0_fwls));
>> }
>> + writel(AUDIO_REFCLK1_DEFAULT,
>> (uintptr_t)CTRL_MMR_CFG0_AUDIO_REFCLK1_CTRL);
>> +
>> /* Output System Firmware version info */
>> k3_sysfw_print_ver();
>> }
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