[PATCH 1/2] clk: mediatek: mt7629: fix gate offset of peri clock tree

[Weijie Gao]

From: Sam Shih <sam.shih at mediatek.com>

The clock definitions in mt7629-clk.h indicate that CLK_PERIBUS_SEL is the
first element in the pericfg clock tree and also serves as a clock mux,
unlike other clocks belonging to the clock gate in pericfg.

This make the clock consumer get a wrong clock gate during request a clock
from <&pericfg>.

Since CLK_PERIBUS_SEL clock is not required in U-Boot, add a clock gate
offset for the pericfg clock tree to resolve this problem.

Signed-off-by: Sam Shih <sam.shih at mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao at mediatek.com>
---
 drivers/clk/mediatek/clk-mt7629.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index 380ab9b9b0b..94fc5e51456 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -574,6 +574,18 @@ static const struct mtk_clk_tree mt7629_clk_tree = {
 	.muxes = top_muxes,
 };
 
+static const struct mtk_clk_tree mt7629_peri_clk_tree = {
+	.xtal_rate = 40 * MHZ,
+	.xtal2_rate = 20 * MHZ,
+	.gates_offs = CLK_PERI_PWM1_PD,
+	.fdivs_offs = CLK_TOP_TO_USB3_SYS,
+	.muxes_offs = CLK_TOP_AXI_SEL,
+	.plls = apmixed_plls,
+	.fclks = top_fixed_clks,
+	.fdivs = top_fixed_divs,
+	.muxes = top_muxes,
+};
+
 static int mt7629_mcucfg_probe(struct udevice *dev)
 {
 	void __iomem *base;
@@ -619,7 +631,7 @@ static int mt7629_infracfg_probe(struct udevice *dev)
 
 static int mt7629_pericfg_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, peri_cgs);
+	return mtk_common_clk_gate_init(dev, &mt7629_peri_clk_tree, peri_cgs);
 }
 
 static int mt7629_ethsys_probe(struct udevice *dev)
-- 
2.34.1