[PATCH] phycore-imx8mp: Enable CAAM in spl

[Leonard Anderweit]

Enable CAAM in spl.

Signed-off-by: Leonard Anderweit <l.anderweit at phytec.de>
---
 board/phytec/phycore_imx8mp/spl.c | 2 ++
 configs/phycore-imx8mp_defconfig  | 2 --
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c
index 0610d8bbd0b8..cb8e450b9956 100644
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -165,6 +165,8 @@ int power_init_board(void)
 
 void spl_board_init(void)
 {
+	arch_misc_init();
+
 	/* Set GIC clock to 500Mhz for OD VDD_SOC. */
 	clock_enable(CCGR_GIC, 0);
 	clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index ba716a6875b8..c0501907b2c4 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -52,7 +52,6 @@ CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
 CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
-# CONFIG_SPL_CRYPTO is not set
 CONFIG_SPL_I2C=y
 CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_POWER=y
@@ -180,4 +179,3 @@ CONFIG_USB_GADGET_MANUFACTURER="PHYTEC"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_IMX_WATCHDOG=y
-# CONFIG_SPL_SHA_HW_ACCEL is not set
-- 
2.34.1