[XGMAC RGMII-ID fix v1 1/1] net: dwc_eth_xgmac_socfpga: Add support for rgmii-id mode.

[Chee, Tien Fong]

> -----Original Message-----
> From: Ng, Boon Khai <boon.khai.ng at intel.com>
> Sent: Friday, January 17, 2025 2:56 PM
> To: Uboot Open List <u-boot at lists.denx.de>
> Cc: Chee, Tien Fong <tien.fong.chee at intel.com>; Hea, Kok Kiang
> <kok.kiang.hea at intel.com>; Maniyam, Dinesh
> <dinesh.maniyam at intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi at intel.com>; Zamri, Muhammad Hazim Izzat
> <muhammad.hazim.izzat.zamri at intel.com>; Tien Fong Chee
> <tien.fong.chee at altera.com>; Kok Kiang Hea <kok.kiang.hea at altera.com>;
> Dinesh Maniyam <dinesh.maniyam at altera.com>; Alif Zakuan
> <alif.zakuan.yuslaimi at altera.com>; Boon Khai Ng
> <boon.khai.ng at altera.com>; Muhammad Hazim
> <muhammad.hazim.izzat.zamri at altera.com>; Joe Hershberger
> <joe.hershberger at ni.com>; Ramon Fried <rfried.dev at gmail.com>; Tom Rini
> <trini at konsulko.com>; Simon Glass <sjg at chromium.org>; Ng, Boon Khai
> <boon.khai.ng at intel.com>
> Subject: [XGMAC RGMII-ID fix v1 1/1] net: dwc_eth_xgmac_socfpga: Add
> support for rgmii-id mode.
> 
> An issue was identified where selecting the phy-mode as rgmii-id in the
> device tree source (DTS) would cause the `dwc_eth_xgmac_socfpga` driver
> to raise an unsupported phy mode error.
> 
> From the MAC controller's perspective, the rgmii and rgmii-id phy modes are
> effectively identical. To address this, both modes will now be configured to
> rgmii in the MAC controller.
> 
> This change ensures that the rgmii-id phy mode is properly supported
> without error.
> 
> Signed-off-by: Boon Khai Ng <boon.khai.ng at intel.com>
> ---
>  drivers/net/dwc_eth_xgmac_socfpga.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/net/dwc_eth_xgmac_socfpga.c
> b/drivers/net/dwc_eth_xgmac_socfpga.c
> index 87fb7e887e..1864187c17 100644
> --- a/drivers/net/dwc_eth_xgmac_socfpga.c
> +++ b/drivers/net/dwc_eth_xgmac_socfpga.c
> @@ -80,6 +80,7 @@ static int xgmac_probe_resources_socfpga(struct
> udevice *dev)
>  		modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
>  		break;
>  	case PHY_INTERFACE_MODE_RGMII:
> +	case PHY_INTERFACE_MODE_RGMII_ID:
>  		modereg =
> SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
>  		break;
>  	default:
> --
> 2.26.2

Reviewed-by: Tien Fong Chee <tien.fong.chee at intel.com>

Best regards,
Tien Fong