[PATCH 0/8] ram: k3-ddrss: Support partial inline ECC

[Neha Malcom Francis]

Currently, the inline ECC implementation enables inline ECC across the
entire DDR space. However this is not always required and a more common
ask is to have only a portion of the DDR protected as enabling ECC
impacts read/write performance metrics.

This series aims to modify the logic to firstly support partial inline
ECC in its' most basic form which works for single controllers. Then it
introduces an algorithm to support multi DDR controllers where
interleaving plays a role. Since interleaving is handled by the MSMC, it
only makes sense to have the MSMC decide the inline ECC ranges for each
DDR.

WIP: A commandline test case patch for verifying the correct behaviour
of inline ECC including partial case. Will add the patch in v2, for now
repeated boot tests on the affected platforms as well as internal
memtester runs stand as testing.

Boot logs (J721S2): https://gist.github.com/nehamalcom/e5a76bece133c1ec716e2ed94d60ce74

Neha Malcom Francis (8):
  k3-ddr.c: Remove unwanted header files
  ram: k3-ddrss: Use DDR address instead of system address for
    ecc_regions
  ram: k3-ddrss: Add comment about ecc_reserved_space
  ram: k3-ddrss: Add support for a partial inline ECC region
  ram: k3-ddrss: Add CONFIG_K3_MULTI_DDR
  ram: k3-ddrss: Add support for number of controllers under MSMC
  ram: k3-ddrss: Add support for MSMC calculation of DDR inline ECC
    regions
  ram: k3-ddrss: Add support for partial inline ECC in multi-DDR systems

 arch/arm/mach-k3/k3-ddr.c       |   1 -
 board/ti/common/k3-ddr.c        |   1 -
 drivers/ram/Kconfig             |  10 ++
 drivers/ram/k3-ddrss/k3-ddrss.c | 227 ++++++++++++++++++++++++++++++--
 4 files changed, 226 insertions(+), 13 deletions(-)

-- 
2.34.1