[PATCH 2/4] xilinx: mbv: Add missing mmu-type cpu property

[Michal Simek]

OpenSBI expects mmu-type to be present in DT that's why add it. Without it
OpenSBI disable CPU node which ends up in not working boot.

Signed-off-by: Michal Simek <michal.simek at amd.com>
---

 arch/riscv/dts/xilinx-mbv32.dts | 3 ++-
 arch/riscv/dts/xilinx-mbv64.dts | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts
index 4050ce2f051d..96e428062442 100644
--- a/arch/riscv/dts/xilinx-mbv32.dts
+++ b/arch/riscv/dts/xilinx-mbv32.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for AMD MicroBlaze V
  *
- * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek at amd.com>
  */
@@ -26,6 +26,7 @@
 			device_type = "cpu";
 			reg = <0>;
 			riscv,isa = "rv32imafdc";
+			mmu-type = "riscv,sv39";
 			i-cache-size = <32768>;
 			d-cache-size = <32768>;
 			clock-frequency = <100000000>;
diff --git a/arch/riscv/dts/xilinx-mbv64.dts b/arch/riscv/dts/xilinx-mbv64.dts
index 4d65d338ecb6..5a989c1697e4 100644
--- a/arch/riscv/dts/xilinx-mbv64.dts
+++ b/arch/riscv/dts/xilinx-mbv64.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for AMD MicroBlaze V
  *
- * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc.
  *
  * Michal Simek <michal.simek at amd.com>
  */
@@ -26,6 +26,7 @@
 			device_type = "cpu";
 			reg = <0>;
 			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
 			i-cache-size = <32768>;
 			d-cache-size = <32768>;
 			clock-frequency = <100000000>;
-- 
2.43.0