[PATCH 3/4] xilinx: mbv: Fix dt properties in interrupt controller node

[Michal Simek]

Properties didn't match dt binding that's why should be fixed.

Signed-off-by: Michal Simek <michal.simek at amd.com>
---

Binding has been sent here:
https://lore.kernel.org/r/6ddaf6f1e3748cdeda2e2e32ee69343a06c60dcb.1753166980.git.michal.simek@amd.com
but it is used for more then 15 years unchanged.
---
 arch/riscv/dts/xilinx-mbv32.dts | 3 ++-
 arch/riscv/dts/xilinx-mbv64.dts | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts
index 96e428062442..b426510f3434 100644
--- a/arch/riscv/dts/xilinx-mbv32.dts
+++ b/arch/riscv/dts/xilinx-mbv32.dts
@@ -71,7 +71,8 @@
 			interrupt-controller;
 			interrupt-parent = <&cpu0_intc>;
 			#interrupt-cells = <2>;
-			kind-of-intr = <0>;
+			xlnx,num-intr-inputs = <2>;
+			xlnx,kind-of-intr = <0>;
 		};
 
 		xlnx_timer0: timer at 41c00000 {
diff --git a/arch/riscv/dts/xilinx-mbv64.dts b/arch/riscv/dts/xilinx-mbv64.dts
index 5a989c1697e4..3762def29f9a 100644
--- a/arch/riscv/dts/xilinx-mbv64.dts
+++ b/arch/riscv/dts/xilinx-mbv64.dts
@@ -71,7 +71,8 @@
 			interrupt-controller;
 			interrupt-parent = <&cpu0_intc>;
 			#interrupt-cells = <2>;
-			kind-of-intr = <0>;
+			xlnx,num-intr-inputs = <2>;
+			xlnx,kind-of-intr = <0>;
 		};
 
 		xlnx_timer0: timer at 41c00000 {
-- 
2.43.0