[PATCH v1 1/2] ARM: tegra: clock: fix PLLD/PLLD2 related clock calculations

[Thierry Reding]

On Wed, Mar 05, 2025 at 03:52:36PM +0200, Svyatoslav Ryhel wrote:
> ср, 5 бер. 2025 р. о 15:47 Thierry Reding <treding at nvidia.com> пише:
> >
> > On Wed, Mar 05, 2025 at 01:12:12PM +0200, Svyatoslav Ryhel wrote:
> > > From: Jonas Schwöbel <jonasschwoebel at yahoo.de>
> > >
> > > While PLLD/D2 is the nominal parent clock, all derived clocks are generated
> > > from its single output, plld_out0, which is PLLD/D2 divided by two. Direct
> > > use of PLLD/D2 is absent in peripheral clock configurations. Therefore,
> > > clock derivation formulas must take in account this division.
> > >
> > > Signed-off-by: Jonas Schwöbel <jonasschwoebel at yahoo.de>
> > > Signed-off-by: Svyatoslav Ryhel <clamor95 at gmail.com>
> > > ---
> > >  arch/arm/mach-tegra/clock.c | 30 +++++++++++++++++++++++++++++-
> > >  1 file changed, 29 insertions(+), 1 deletion(-)
> >
> > In Linux we ended up exposing the _out0 branches of the display clocks.
> > Wouldn't that be a better way to describe this?
> >
> > Thierry
> 
> You are not satisfied with the description or with solution?

I meant the solution. However I might have misunderstood what you're
doing here. This is actually computing the rate of the _out0 branches,
which are the ones listed in the DTS files as parents, correct?

Thierry
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