[PATCH] spi: cadence_ospi: Add device reset via OSPI controller

[Michal Simek]

On 3/10/25 09:03, Michal Simek wrote:
> 
> 
> On 2/20/25 15:19, Venkatesh Yadav Abbarapu wrote:
>> Add support for flash device reset via OSPI controller
>> instead of using GPIO, as OSPI IP has device reset
>> feature on Versal Gen2 platform. Also add compatible
>> string for Versal Gen2 platform.
>>
>> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu at amd.com>
>> ---
>>   drivers/spi/cadence_ospi_versal.c | 19 +++++++++++++++++++
>>   drivers/spi/cadence_qspi.c        |  4 ++++
>>   drivers/spi/cadence_qspi.h        |  4 +++-
>>   3 files changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/ 
>> cadence_ospi_versal.c
>> index 816916de16d..fbeb0c6a85c 100644
>> --- a/drivers/spi/cadence_ospi_versal.c
>> +++ b/drivers/spi/cadence_ospi_versal.c
>> @@ -204,3 +204,22 @@ void cadence_qspi_apb_enable_linear_mode(bool enable)
>>                      ~VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL);
>>       }
>>   }
>> +
>> +int cadence_device_reset(struct udevice *bus)
>> +{
>> +    struct cadence_spi_priv *priv = dev_get_priv(bus);
>> +    u32 reg;
>> +
>> +    reg = readl(priv->regbase + CQSPI_REG_CONFIG);
>> +    reg |= CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK;
>> +    writel(reg, priv->regbase + CQSPI_REG_CONFIG);
>> +
>> +    writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + 
>> CQSPI_REG_CONFIG);
>> +    udelay(5);
>> +    writel(reg | CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + 
>> CQSPI_REG_CONFIG);
>> +    udelay(150);
>> +    writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + 
>> CQSPI_REG_CONFIG);
>> +    udelay(1200);
>> +
>> +    return 0;
>> +}
>> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
>> index 623904ecdad..05356ad2e03 100644
>> --- a/drivers/spi/cadence_qspi.c
>> +++ b/drivers/spi/cadence_qspi.c
>> @@ -251,6 +251,9 @@ static int cadence_spi_probe(struct udevice *bus)
>>       priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
>> +    if (device_is_compatible(bus, "amd,versal2-ospi"))
>> +        return cadence_device_reset(bus);
>> +
>>       /* Reset ospi flash device */
>>       return cadence_qspi_flash_reset(bus);
>> @@ -452,6 +455,7 @@ static const struct dm_spi_ops cadence_spi_ops = {
>>   static const struct udevice_id cadence_spi_ids[] = {
>>       { .compatible = "cdns,qspi-nor" },
>>       { .compatible = "ti,am654-ospi" },
>> +    { .compatible = "amd,versal2-ospi" },
>>       { }
>>   };
>> diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
>> index 1f9125cd239..d7db37c1463 100644
>> --- a/drivers/spi/cadence_qspi.h
>> +++ b/drivers/spi/cadence_qspi.h
>> @@ -45,6 +45,8 @@
>>   #define CQSPI_REG_CONFIG_CLK_POL                BIT(1)
>>   #define CQSPI_REG_CONFIG_CLK_PHA                BIT(2)
>>   #define CQSPI_REG_CONFIG_PHY_ENABLE_MASK        BIT(3)
>> +#define CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK    BIT(5)
>> +#define CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK    BIT(6)
>>   #define CQSPI_REG_CONFIG_DIRECT                 BIT(7)
>>   #define CQSPI_REG_CONFIG_DECODE                 BIT(9)
>>   #define CQSPI_REG_CONFIG_ENBL_DMA               BIT(15)
>> @@ -310,5 +312,5 @@ int cadence_qspi_apb_exec_flash_cmd(void *reg_base, 
>> unsigned int reg);
>>   int cadence_qspi_flash_reset(struct udevice *dev);
>>   ofnode cadence_qspi_get_subnode(struct udevice *dev);
>>   void cadence_qspi_apb_enable_linear_mode(bool enable);
>> -
>> +int cadence_device_reset(struct udevice *dev);
> 
> This newline is nice. Anyway I have patched it.
> 
>>   #endif /* __CADENCE_QSPI_H__ */
> 
> Applied with small change in commit message to spell Versal Gen 2 properly.

CI found build issue for.

phycore_am62ax_a53_defconfig

That's why dropping this patch from my queue and please send v2 of this also 
with above changes.

Thanks,
Michal