[PATCH 1/2] spi: zynqmp_gqspi: Make WR_ANY_REG opcode not use striped access

[tkuw584924 at gmail.com]

From: Takahiro Kuwano <Takahiro.Kuwano at infineon.com>

SPINOR_OP_WR_ANY_REG (0x71) opcode must not be performed in striped
access mode to write the same register value to two Flash devices in
parallel memory configuration. The opcde 0x71 is also used as Read
Configuration Register-2 (SPINOR_OP_RD_CR2). To distiguish it, data
direction needs to be checked.

The following commit is related to this patch.
217b0a28b6d ("spi: zynqmp_gqspi: Add parallel memories support in GQSPI driver")

Tested-by: Hiroyuki Saito <Hiroyuki.Saito2 at infineon.com> 
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano at infineon.com>
---
 drivers/spi/zynqmp_gqspi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 2a095d0c58e..f47c3058942 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -841,6 +841,8 @@ static bool zynqmp_qspi_update_stripe(const struct spi_mem_op *op)
 		return false;
 	case SPINOR_OP_WRSR2:
 		return op->addr.nbytes != 0;
+	case SPINOR_OP_WR_ANY_REG:
+		return op->data.dir != SPI_MEM_DATA_OUT;
 	default:
 		return true;
 	}
-- 
2.34.1