[PATCH 3/3] clk/qcom: sc7280: add GENI, PCIe, and more USB clocks
Neil Armstrong
neil.armstrong at linaro.org
Mon Mar 17 15:03:09 CET 2025
On 14/03/2025 16:31, Caleb Connolly wrote:
> Add support for a bunch of new clocks, including PCIe, GENI (for all
> peripherals used on the RB3 Gen 2), and some missing USB clocks.
>
> Signed-off-by: Caleb Connolly <caleb.connolly at linaro.org>
> ---
> drivers/clk/qcom/clock-sc7280.c | 104 +++++++++++++++++++++++++++++++++++-----
> 1 file changed, 93 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
> index 2cbc01b6e0a4f1db0e4a894cd869b532d6b3fa45..8691f08109b39639d8a5defe75161049399bf682 100644
> --- a/drivers/clk/qcom/clock-sc7280.c
> +++ b/drivers/clk/qcom/clock-sc7280.c
> @@ -15,31 +15,66 @@
> #include <dt-bindings/clock/qcom,gcc-sc7280.h>
>
> #include "clock-qcom.h"
>
> -#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
> #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
> +#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
> +#define USB30_SEC_MASTER_CLK_CMD_RCGR 0x9e020
> +#define USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR 0x9e038
> +#define PCIE_1_AUX_CLK_CMD_RCGR 0x8d058
> +#define PCIE1_PHY_RCHNG_CMD_RCGR 0x8d03c
> +#define PCIE_1_PIPE_CLK_PHY_MUX 0x8d054
> +
> +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
> + F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
> + F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
> + F(200000000, CFG_CLK_SRC_GPLL0_ODD, 1, 0, 0),
> + F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
> + { }
> +};
> +
> +static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk_src[] = {
> + F(60000000, CFG_CLK_SRC_GPLL0_EVEN, 5, 0, 0),
> + F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
> + { }
> +};
>
> static ulong sc7280_set_rate(struct clk *clk, ulong rate)
> {
> struct msm_clk_priv *priv = dev_get_priv(clk->dev);
> + const struct freq_tbl *freq;
>
> if (clk->id < priv->data->num_clks)
> debug("%s: %s, requested rate=%ld\n", __func__, priv->data->clks[clk->id].name, rate);
>
> switch (clk->id) {
> - case GCC_USB30_PRIM_MOCK_UTMI_CLK:
> - WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate);
> - clk_rcg_set_rate(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
> - return rate;
> case GCC_USB30_PRIM_MASTER_CLK:
> - WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
> + freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
> clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
> - 1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
> - clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
> - return rate;
> + freq->pre_div, freq->m, freq->n, freq->src, 8);
> + return freq->freq;
> + case GCC_USB30_PRIM_MOCK_UTMI_CLK:
> + clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
> + return 19200000;
> + case GCC_USB3_PRIM_PHY_AUX_CLK_SRC:
> + clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
> + return 19200000;
> + case GCC_USB30_SEC_MASTER_CLK:
> + freq = qcom_find_freq(ftbl_gcc_usb30_sec_master_clk_src, rate);
> + clk_rcg_set_rate_mnd(priv->base, USB30_SEC_MASTER_CLK_CMD_RCGR,
> + freq->pre_div, freq->m, freq->n, freq->src, 8);
> + return freq->freq;
> + case GCC_USB30_SEC_MOCK_UTMI_CLK:
> + clk_rcg_set_rate(priv->base, USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
> + return 19200000;
> + case GCC_USB3_SEC_PHY_AUX_CLK_SRC:
> + clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
> + return 19200000;
> + case GCC_PCIE1_PHY_RCHNG_CLK:
> + clk_rcg_set_rate(priv->base, PCIE1_PHY_RCHNG_CMD_RCGR, 5, CFG_CLK_SRC_GPLL0_EVEN);
> + return 100000000;
> default:
> - return 0;
> + return rate;
> }
> }
>
> static const struct gate_clk sc7280_clks[] = {
> @@ -49,15 +84,37 @@ static const struct gate_clk sc7280_clks[] = {
> GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0xf018, 1),
> GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, 1),
> GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, 1),
> GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, 1),
> + GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x9e07c, 1),
> + GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x9e010, 1),
> + GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x9e080, 1),
> + GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x9e018, 1),
> + GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x9e01c, 1),
> + GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x9e054, 1),
> + GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x9e058, 1),
> + GATE_CLK(GCC_PCIE_CLKREF_EN, 0x8c004, 1),
> + GATE_CLK(GCC_PCIE_1_PIPE_CLK, 0x52000, BIT(30)),
> + GATE_CLK(GCC_PCIE_1_AUX_CLK, 0x52000, BIT(29)),
> + GATE_CLK(GCC_PCIE_1_CFG_AHB_CLK, 0x52000, BIT(28)),
> + GATE_CLK(GCC_PCIE_1_MSTR_AXI_CLK, 0x52000, BIT(27)),
> + GATE_CLK(GCC_PCIE_1_SLV_AXI_CLK, 0x52000, BIT(26)),
> + GATE_CLK(GCC_PCIE_1_SLV_Q2A_AXI_CLK, 0x52000, BIT(25)),
> + GATE_CLK(GCC_PCIE1_PHY_RCHNG_CLK, 0x52000, BIT(23)),
> + GATE_CLK(GCC_DDRSS_PCIE_SF_CLK, 0x52000, BIT(19)),
> + GATE_CLK(GCC_AGGRE_NOC_PCIE_TBU_CLK, 0x52000, BIT(18)),
> + GATE_CLK(GCC_AGGRE_NOC_PCIE_1_AXI_CLK, 0x52000, BIT(11)),
> + GATE_CLK(GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK, 0x52008, BIT(28)),
> + GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, BIT(10)),
> + GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, BIT(11)),
> + GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, BIT(13)),
> };
>
> static int sc7280_enable(struct clk *clk)
> {
> struct msm_clk_priv *priv = dev_get_priv(clk->dev);
>
> - if (priv->data->num_clks < clk->id) {
> + if (priv->data->num_clks <= clk->id) {
> debug("%s: unknown clk id %lu\n", __func__, clk->id);
> return 0;
> }
>
> @@ -70,8 +127,31 @@ static int sc7280_enable(struct clk *clk)
> case GCC_USB30_PRIM_MASTER_CLK:
> qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
> qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
> break;
> + case GCC_AGGRE_USB3_SEC_AXI_CLK:
> + qcom_gate_clk_en(priv, GCC_USB30_SEC_MASTER_CLK);
> + fallthrough;
> + case GCC_USB30_SEC_MASTER_CLK:
> + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK);
> + qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
> + break;
> + case GCC_PCIE_1_PIPE_CLK:
> + clk_phy_mux_enable(priv->base, PCIE_1_PIPE_CLK_PHY_MUX, true);
> + break;
> + case GCC_PCIE_1_AUX_CLK:
> + clk_rcg_set_rate_mnd(priv->base, PCIE_1_AUX_CLK_CMD_RCGR, 1, 0, 0,
> + CFG_CLK_SRC_CXO, 16);
> + break;
> + case GCC_QUPV3_WRAP0_S0_CLK:
> + clk_rcg_set_rate_mnd(priv->base, 0x17010, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
> + break;
> + case GCC_QUPV3_WRAP0_S1_CLK:
> + clk_rcg_set_rate_mnd(priv->base, 0x17140, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
> + break;
> + case GCC_QUPV3_WRAP0_S3_CLK:
> + clk_rcg_set_rate_mnd(priv->base, 0x173a0, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
> + break;
> }
>
> return qcom_gate_clk_en(priv, clk->id);
> }
> @@ -97,8 +177,10 @@ static const struct qcom_reset_map sc7280_gcc_resets[] = {
>
> static const struct qcom_power_map sc7280_gdscs[] = {
> [GCC_UFS_PHY_GDSC] = { 0x77004 },
> [GCC_USB30_PRIM_GDSC] = { 0xf004 },
> + [GCC_USB30_SEC_GDSC] = { 0x9e004 },
> + [GCC_PCIE_1_GDSC] = { 0x8d004 },
> };
>
> static const phys_addr_t sc7280_rcg_addrs[] = {
> 0x10f020, // USB30_PRIM_MASTER_CLK_CMD_RCGR
>
Reviewed-by: Neil Armstrong <neil.armstrong at linaro.org>
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