[PATCH 4/5] ram: renesas: dbsc5: Factor out dbsc5_wait_dbwait()

[Marek Vasut]

Extract wait for completion code from dbsc5_send_dbcmd2() into
new separate function dbsc5_wait_dbwait(). This extracted code
can be used to implement MR register read in the future.

Signed-off-by: Marek Vasut <marek.vasut+renesas at mailbox.org>
---
Cc: Nobuhiro Iwamatsu <iwamatsu at nigauri.org>
Cc: Tom Rini <trini at konsulko.com>
Cc: u-boot at lists.denx.de
---
 drivers/ram/renesas/dbsc5/dram.c | 42 ++++++++++++++++++++++----------
 1 file changed, 29 insertions(+), 13 deletions(-)

diff --git a/drivers/ram/renesas/dbsc5/dram.c b/drivers/ram/renesas/dbsc5/dram.c
index 461c862ea27..ce04dd58180 100644
--- a/drivers/ram/renesas/dbsc5/dram.c
+++ b/drivers/ram/renesas/dbsc5/dram.c
@@ -1740,6 +1740,34 @@ static void dbsc5_reg_write(void __iomem *addr, u32 data)
 		writel(data, addr + 0x8000);
 }
 
+/**
+ * dbsc5_wait_dbwait() - DRAM Command Wait Access Completion
+ * @dev: DBSC5 device
+ *
+ * Wait for DRAM access completion. This is used before sending a command
+ * to the DRAM to assure no other command is in flight already, or while
+ * waiting for MRR command to complete.
+ */
+static void dbsc5_wait_dbwait(struct udevice *dev)
+{
+	struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
+	void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET;
+	u32 val;
+	int ret;
+
+	ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBWAIT, val, ((val & BIT(0)) == 0), 1000000);
+	if (ret < 0) {
+		printf("%s DBWAIT bit 0 timeout\n", __func__);
+		hang();
+	}
+
+	ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBWAIT + 0x4000, val, ((val & BIT(0)) == 0), 1000000);
+	if (ret < 0) {
+		printf("%s DBWAIT + 0x4000 bit 0 timeout\n", __func__);
+		hang();
+	}
+}
+
 /**
  * dbsc5_send_dbcmd2() - DRAM Command Write Access
  * @dev: DBSC5 device
@@ -1759,23 +1787,11 @@ static void dbsc5_send_dbcmd2(struct udevice *dev, const u8 opcode,
 	const u32 cmd = (opcode << 24) | (channel << 20) | (rank << 16) | arg;
 	struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
 	void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET;
-	u32 val;
-	int ret;
 
 	/* dummy read */
 	readl(regs_dbsc_d + DBSC_DBCMD);
 
-	ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBWAIT, val, ((val & BIT(0)) == 0), 1000000);
-	if (ret < 0) {
-		printf("%s DBWAIT bit 0 timeout\n", __func__);
-		hang();
-	}
-
-	ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBWAIT + 0x4000, val, ((val & BIT(0)) == 0), 1000000);
-	if (ret < 0) {
-		printf("%s DBWAIT + 0x4000 bit 0 timeout\n", __func__);
-		hang();
-	}
+	dbsc5_wait_dbwait(dev);
 
 	dbsc5_reg_write(regs_dbsc_d + DBSC_DBCMD, cmd);
 }
-- 
2.47.2