[PATCH 1/1] riscv: dts: jh7110: add bootph-pre-ram for &pllclk

[Heinrich Schuchardt]

Since commit f98cd471f06b ("clk: clk-composite: Resolve parent clock by
name") the StarFive VisionFive 2 board fails to boot.

Before that patch the SPL debug UART showed warnings like:

    clk_register: failed to get pll0_out device (parent of perh_root)
    clk_register: failed to get pll0_out device (parent of qspi_ref_src)
    clk_register: failed to get pll0_out device (parent of usb_125m)
    clk_register: failed to get pll0_out device (parent of gmac_src)
    clk_register: failed to get pll0_out device (parent of gmac1_gtxclk)
    clk_register: failed to get pll0_out device (parent of gmac0_gtxclk)

The &pllclk clock needs to be enabled early.

Fixes: f98cd471f06b ("clk: clk-composite: Resolve parent clock by name")
Suggested-by: Marek Vasut <marex at denx.de>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
 arch/riscv/dts/jh7110-u-boot.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index ce7d9e16961..a9e318c4a31 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -102,6 +102,10 @@
 	bootph-pre-ram;
 };
 
+&pllclk {
+	bootph-pre-ram;
+};
+
 &syscrg {
 	bootph-pre-ram;
 };
-- 
2.48.1